公开(公告)号：US11942904B2

公开(公告)日：2024-03-26

申请号：US17402892

申请日：2021-08-16

Applicant: Xilinx, Inc.

Inventor： Hongzhi Zhao ,  Xing Zhao ,  Vincent C. Barnes ,  Xiaohan Chen ,  Hemang M. Parekh

IPC: H03F1/32 ,  H03F3/21 ,  H03G1/00

CPC classification number: H03F1/3247 ,  H03F3/21 ,  H03G1/0005 ,  H03F2201/3227

Abstract: A digital predistortion (DPD) system includes an input configured to receive an input signal. In some examples, a first signal path configured to generate a first signal based on the input signal. In some examples, an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system. In some examples, a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal, and the DPD system generates an output signal based at least on the first intermediate signal.

公开(公告)号：US11984919B2

公开(公告)日：2024-05-14

申请号：US17959079

申请日：2022-10-03

Applicant: XILINX, INC.

Inventor： Hongzhi Zhao ,  Christophe Erdmann ,  Hemang M. Parekh ,  Xing Zhao ,  Xiaohan Chen

IPC: H04B1/12 ,  H04L27/01

CPC classification number: H04B1/123 ,  H04L27/01

Abstract: Embodiments herein describe a PIM correction circuit. In a base station, TX and RX RF changes, band pass filters, duplexers, and diplexers can have severe memory effects due to their sharp transition bandwidth from pass band to stop band. PIM interference, generated by the TX signals and reflected onto the RX RF chain will include these memory effects. These memory effects make PIM cancellation complex, requiring complicated computations and circuits. However, the embodiments herein use a PIM correction circuit that separates the memory effects of the TX and RX paths from the memory effects of PIM, thereby reducing PIM cancellation complexity and hardware implementation cost.

公开(公告)号：US20230046588A1

公开(公告)日：2023-02-16

申请号：US17402892

申请日：2021-08-16

Applicant: Xilinx, Inc.

Inventor： Hongzhi Zhao ,  Xing Zhao ,  Vincent C. Barnes ,  Xiaohan Chen ,  Hemang M. Parekh

IPC: H03F1/32 ,  H03G1/00 ,  H03F3/21

Abstract: A digital predistortion (DPD) system includes an input configured to receive an input signal. In some examples, a first signal path configured to generate a first signal based on the input signal. In some examples, an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system. In some examples, a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal, and the DPD system generates an output signal based at least on the first intermediate signal.