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公开(公告)号:US20250081668A1
公开(公告)日:2025-03-06
申请号:US18803566
申请日:2024-08-13
Applicant: XINTEC INC.
Inventor: Wei-Luen SUEN , Po-Jung CHEN , Jiun-Yen LAI , Tsang Yu LIU
IPC: H01L31/02 , H01L21/66 , H01L31/0216 , H01L31/18
Abstract: A chip package includes a semiconductor substrate, an anti-reflection layer, and a metal multi-layer. The semiconductor substrate has an optical sensing area. The anti-reflection layer is located on the semiconductor substrate. The metal multi-layer is located on and in contact with the anti-reflection layer. The metal multi-layer includes a redistribution line and two probe pads. Two ends of the redistribution line respectively extend to the two probe pads. The redistribution line is located in the optical sensing area, and the two probe pads are located outside the optical sensing area. The orthographic projection area of the redistribution line in the optical sensing area is less than 1% of the area of the optical sensing area.
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公开(公告)号:US20250054849A1
公开(公告)日:2025-02-13
申请号:US18779105
申请日:2024-07-22
Applicant: Xintec Inc.
Inventor: Wei-Luen SUEN , Po-Jung CHEN , Chia-Ming CHENG , Po-Shen LIN , Jiun-Yen LAI , Tsang-Yu LIU , Shu-Ming CHANG
IPC: H01L23/498 , H01L21/768 , H01L23/15 , H01L23/528
Abstract: A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.
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