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    CHIP PACKAGE
    1.
    发明申请
    CHIP PACKAGE 有权

    公开(公告)号：US20230049126A1

    公开(公告)日：2023-02-16

    申请号：US17980507

    申请日：2022-11-03

    Applicant: XINTEC INC.

    Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

    IPC: H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56

    Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210210445A1

    公开(公告)日：2021-07-08

    申请号：US17140952

    申请日：2021-01-04

    Applicant: XINTEC INC.

    Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

    IPC: H01L23/66 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56

    Abstract: A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20140332985A1

    公开(公告)日：2014-11-13

    申请号：US14341573

    申请日：2014-07-25

    Applicant: XINTEC INC.

    Inventor： Ching-Yu NI ,  Chia-Ming CHENG ,  Nan-Chun LIN

    IPC: H01L23/498

    CPC classification number: H01L23/498 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/06 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

    Abstract translation: 根据本发明的实施例提供了芯片封装及其制造方法。 芯片封装包括含有芯片并具有器件面积和外围焊盘区域的半导体衬底。 多个导电焊盘设置在外围接合焊盘区域处，并且钝化层形成在半导体衬底上以露出导电焊盘。 在器件区域的钝化层上形成绝缘保护层。 封装层设置在绝缘保护层上方以在外围接合焊盘区域露出导电焊盘和钝化层。 该方法包括在切割过程中形成绝缘保护层以覆盖多个导电焊盘，并且通过封装层的开口去除导电焊盘上的绝缘保护层。

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    4.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20140113412A1

    公开(公告)日：2014-04-24

    申请号：US14135506

    申请日：2013-12-19

    Applicant: XINTEC INC.

    Inventor： Chia-Lun TSAI ,  Chia-Ming CHENG ,  Long-Sheng YEOU

    IPC: H01L21/78

    CPC classification number: H01L21/78 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00825 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0118

    Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

    Abstract translation: 本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层， 形成随后的半导体制造工艺的开口。

    CHIP PACKAGE
    5.
    发明申请
    CHIP PACKAGE 有权

    公开(公告)号：US20210210436A1

    公开(公告)日：2021-07-08

    申请号：US17140964

    申请日：2021-01-04

    Applicant: XINTEC INC.

    Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

    IPC: H01L23/552 ,  H01L23/528 ,  H01L23/66

    Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210082841A1

    公开(公告)日：2021-03-18

    申请号：US17023199

    申请日：2020-09-16

    Applicant: XINTEC INC.

    Inventor： Po-Han LEE ,  Chia-Ming CHENG ,  Jiun-Yen LAI ,  Ming-Chung CHUNG ,  Wei-Luen SUEN

    IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L21/3213

    Abstract: A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190140012A1

    公开(公告)日：2019-05-09

    申请号：US16178483

    申请日：2018-11-01

    Applicant: XINTEC INC.

    Inventor： Hsin KUAN ,  Shih-Kuang CHEN ,  Chin-Ching HUANG ,  Chia-Ming CHENG

    IPC: H01L27/146 ,  H01L23/00 ,  H01L21/56

    Abstract: A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.

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