公开(公告)号：USD953066S1

公开(公告)日：2022-05-31

申请号：US29727829

申请日：2020-03-13

Applicant: Xiaopeng Yu

Designer： Xiaopeng Yu

公开(公告)号：US20080318382A1

公开(公告)日：2008-12-25

申请号：US11956005

申请日：2007-12-13

Applicant: Peigang Dai ,  Xiaopeng Yu ,  Jing Lin ,  Hualong Song

Inventor： Peigang Dai ,  Xiaopeng Yu ,  Jing Lin ,  Hualong Song

IPC: H01L21/336 ,  H01L21/283

CPC classification number: H01L29/66825 ,  H01L29/40114

Abstract: A method for manufacturing a tunneling oxide layer including the following steps: forming a tunneling oxide layer on a semiconductor substrate by in-situ steam generation oxidation; performing a annealing on the tunneling oxide layer. There is also provided a method for manufacturing a flash memory device. According to the invention, the dangling bonds between silicon oxide in a tunneling oxide layer and silicon adjacent to a semiconductor substrate interface are terminated by performing a annealing on a tunneling oxide layer, thereby improving the erase rate of the tunneling oxide layer.

Abstract translation: 一种隧道氧化层的制造方法，包括以下步骤：通过原位蒸汽发生氧化在半导体基板上形成隧道氧化物层; 对隧道氧化物层进行退火。 还提供了一种用于制造闪存装置的方法。 根据本发明，通过对隧道氧化物层进行退火来终止隧道氧化物层中的氧化硅与与半导体衬底界面相邻的硅之间的悬挂键，从而提高隧道氧化物层的擦除速率。

公开(公告)号：US07851383B2

公开(公告)日：2010-12-14

申请号：US12052640

申请日：2008-03-20

Applicant: Xiaopeng Yu ,  Sean F. Zhang

Inventor： Xiaopeng Yu ,  Sean F. Zhang

IPC: H01L21/31

CPC classification number: H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Method and system for forming gate structure with controllable oxide. The method includes a step for providing a semiconductor substrate and defining a source region and a drain region within the semiconductor substrate. Furthermore, the method includes a step for defining a gate region positioned between the source region and the drain region. Moreover, the method provides a step for forming a first layer overlaying the gate region. The first layer includes silicon nitride and/or silicon oxynitride material. Also, the method includes a step for forming a second layer by subjecting the semiconductor substrate to at least oxygen at a predetermined temperature range for a period of time. The second layer has a thickness less than 20 Angstroms.

Abstract translation: 用可控氧化物形成栅极结构的方法和系统 该方法包括提供半导体衬底并限定半导体衬底内的源极区和漏极区的步骤。 此外，该方法包括用于限定位于源极区域和漏极区域之间的栅极区域的步骤。 此外，该方法提供了形成覆盖栅极区域的第一层的步骤。 第一层包括氮化硅和/或氮氧化硅材料。 此外，该方法包括通过使半导体衬底至少在预定温度范围内的氧持续一段时间来形成第二层的步骤。 第二层的厚度小于20埃。

公开(公告)号：US20080233692A1

公开(公告)日：2008-09-25

申请号：US12052640

申请日：2008-03-20

Applicant: Xiaopeng Yu ,  Sean F. Zhang

Inventor： Xiaopeng Yu ,  Sean F. Zhang

IPC: H01L21/336

CPC classification number: H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Method and system for forming gate structure with controllable oxide. The method includes a step for providing a semiconductor substrate and defining a source region and a drain region within the semiconductor substrate. Furthermore, the method includes a step for defining a gate region positioned between the source region and the drain region. Moreover, the method provides a step for forming a first layer overlaying the gate region. The first layer includes silicon nitride and/or silicon oxynitride material. Also, the method includes a step for forming a second layer by subjecting the semiconductor substrate to at least oxygen at a predetermined temperature range for a period of time. The second layer has a thickness less than 20 Angstroms.

Abstract translation: 用可控制的氧化物形成栅极结构的方法和系统。 该方法包括提供半导体衬底并限定半导体衬底内的源极区域和漏极区域的步骤。 此外，该方法包括用于限定位于源极区域和漏极区域之间的栅极区域的步骤。 此外，该方法提供了形成覆盖栅极区域的第一层的步骤。 第一层包括氮化硅和/或氮氧化硅材料。 此外，该方法包括通过使半导体衬底至少在预定温度范围内的氧持续一段时间来形成第二层的步骤。 第二层的厚度小于20埃。