公开(公告)号：US20230289500A1

公开(公告)日：2023-09-14

申请号：US17692602

申请日：2022-03-11

Applicant: Xilinx, Inc.

Inventor： Anindita Patra ,  Ali Behboodian ,  Michael Gill

IPC: G06F30/31

CPC classification number: G06F30/31

Abstract: Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications based on one of the types of programming model into an accelerator representation. The design tool can generate a build script configured to execute the compiler scripts and link the accelerator representations into linked accelerator representations. Execution of the build script builds a hardware image from the linked accelerator representations for configuring the programmable IC to implement a circuit according to the circuit design.

公开(公告)号：US12073155B2

公开(公告)日：2024-08-27

申请号：US17692602

申请日：2022-03-11

Applicant: Xilinx, Inc.

Inventor： Anindita Patra ,  Ali Behboodian ,  Michael Gill

IPC: G06F30/31 ,  G06F30/34

CPC classification number: G06F30/31 ,  G06F30/34

Abstract: Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications based on one of the types of programming model into an accelerator representation. The design tool can generate a build script configured to execute the compiler scripts and link the accelerator representations into linked accelerator representations. Execution of the build script builds a hardware image from the linked accelerator representations for configuring the programmable IC to implement a circuit according to the circuit design.

公开(公告)号：US11270051B1

公开(公告)日：2022-03-08

申请号：US17092875

申请日：2020-11-09

Applicant: Xilinx, Inc.

Inventor： Avinash Somalinga Suresh ,  Ali Behboodian

IPC: G06F30/00 ,  G06F30/327 ,  G06F30/398 ,  G06F30/3953 ,  G06F30/392

Abstract: Model-based implementation of a design for a heterogeneous integrated circuit can include converting a model, created as a data structure using a modeling system, into a data flow graph, wherein the model represents a design for implementation in an integrated circuit having a plurality of systems, the systems being heterogeneous, classifying nodes of the data flow graph for implementation in different ones of the plurality of systems of the integrated circuit, and partitioning the data flow graph into a plurality of sub-graphs based on the classifying, wherein each sub-graph corresponds to a different one of the plurality of systems. From each sub-graph, a portion of high-level language (HLL) program code can be generated. Each portion of HLL program code may be specific to the system corresponding to the sub-graph from which the portion of HLL program code was generated.

公开(公告)号：US10706193B1

公开(公告)日：2020-07-07

申请号：US16209724

申请日：2018-12-04

Applicant: Xilinx, Inc.

Inventor： David Van Campenhout ,  Avinash Somalinga Suresh ,  Ali Behboodian

IPC: G06F30/30 ,  G06F30/33 ,  G06F30/392

Abstract: Approaches for simulating and processing a circuit design involve recognizing by a design processing tool a replaceable subsystem in a circuit design having multiple blocks. The replaceable subsystem includes a subset of the blocks. The design tool converts the subset of blocks into an executable program and schedules activation of blocks of the circuit design other than the subset of blocks during simulation of the circuit design. The scheduled blocks are activated during simulation according to the scheduling, and activation of the subset of the plurality of blocks is bypassed during simulation with a call to the executable program.