公开(公告)号：US12073155B2

公开(公告)日：2024-08-27

申请号：US17692602

申请日：2022-03-11

Applicant: Xilinx, Inc.

Inventor： Anindita Patra ,  Ali Behboodian ,  Michael Gill

IPC: G06F30/31 ,  G06F30/34

CPC classification number: G06F30/31 ,  G06F30/34

Abstract: Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications based on one of the types of programming model into an accelerator representation. The design tool can generate a build script configured to execute the compiler scripts and link the accelerator representations into linked accelerator representations. Execution of the build script builds a hardware image from the linked accelerator representations for configuring the programmable IC to implement a circuit according to the circuit design.

公开(公告)号：US09881117B1

公开(公告)日：2018-01-30

申请号：US15204883

申请日：2016-07-07

Applicant: Xilinx, Inc.

Inventor： Anindita Patra ,  Nabeel Shirazi

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A method for creating a circuit design for an integrated circuit includes, responsive to a request to modify a current circuit design, determining, using a processor, a first core used in the current circuit design and predicting, using the processor, a second core not yet included in the current circuit design as a candidate core for inclusion in the current circuit design. The second core is determined based upon usage of the second core and the first core, in combination, in a plurality of example circuit designs.

公开(公告)号：US20230289500A1

公开(公告)日：2023-09-14

申请号：US17692602

申请日：2022-03-11

Applicant: Xilinx, Inc.

Inventor： Anindita Patra ,  Ali Behboodian ,  Michael Gill

IPC: G06F30/31

CPC classification number: G06F30/31

Abstract: Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications based on one of the types of programming model into an accelerator representation. The design tool can generate a build script configured to execute the compiler scripts and link the accelerator representations into linked accelerator representations. Execution of the build script builds a hardware image from the linked accelerator representations for configuring the programmable IC to implement a circuit according to the circuit design.

公开(公告)号：US10977401B1

公开(公告)日：2021-04-13

申请号：US16724553

申请日：2019-12-23

Applicant: Xilinx, Inc.

Inventor： Jeffrey M. Arnold ,  Stephen L. Bade ,  Srinivas Beeravolu ,  Chukwuweta Chukwudebe ,  Anindita Patra ,  Nabeel Shirazi

IPC: G06F30/327 ,  G06F30/343 ,  G06F30/398

Abstract: Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.