公开(公告)号：US20250103783A1

公开(公告)日：2025-03-27

申请号：US18371937

申请日：2023-09-22

Applicant: Xilinx, Inc.

Inventor： Alok Mistry ,  Anil Kumar A V

IPC: G06F30/3308

Abstract: A system-on-chip (SoC) has programmable logic and a processor. A design tool generates configuration data to implement circuitry for emulation of a design-under-test (DUT) on the programmable logic and generates testbench executable code. The testbench executable code is configured to generate stimuli to the circuitry on the programmable logic. The processor can be configured to execute the testbench executable code and the programmable logic can be configured to implement the circuitry for emulation of the DUT.

公开(公告)号：US20240419878A1

公开(公告)日：2024-12-19

申请号：US18211465

申请日：2023-06-19

Applicant: Xilinx, Inc.

Inventor： Anil Kumar A V ,  Alok Mistry

IPC: G06F30/327 ,  G06F30/31 ,  G06F30/323

Abstract: A method, system, and circuit arrangement involve synthesizing a circuit design specified in a register transfer level (RTL) specification into a netlist. The RTL specification includes an assert statement that specifies a conditional expression involving one or more signals specified in the circuit design to be checked during simulation, and the synthesizing includes synthesizing the assert statement into netlist elements. The design tool places and routes the netlist into a circuit design layout and generates implementation data from the layout.

公开(公告)号：US20240354478A1

公开(公告)日：2024-10-24

申请号：US18137207

申请日：2023-04-20

Applicant: Xilinx, Inc.

Inventor： Alok Mistry ,  Niloy Roy ,  Shanish Chandra Mishra ,  Anil Kumar A V

IPC: G06F30/33 ,  G06F30/327

CPC classification number: G06F30/33 ,  G06F30/327

Abstract: Disclosed methods and systems include debug circuitry registering candidate sample values in a plurality of sample periods while application circuitry is active. The candidate sample values indicate states of a plurality of candidate signals of the application circuitry. Sample values of first probed signals from each sample period are written to a sample memory using a mapping based on bit-widths of the first probed signals. The sample values of the first probed signals are selected from the candidate sample values. The mapping is updated based on bit-widths of second probed signals, and sample values of the second probed signals from each sample period are written to the sample memory using the mapping. The sample values of the second probed signals are selected from the candidate sample values.