公开(公告)号：US10445219B1

公开(公告)日：2019-10-15

申请号：US15839735

申请日：2017-12-12

Applicant: Xilinx, Inc.

Inventor： Niloy Roy ,  Jake Chang ,  Bradley K. Fross

IPC: G06F11/36 ,  G06F11/34

Abstract: Extracting transaction level information from an interface can include tracking transactions of an interface within an integrated circuit (IC) using a plurality of counters within the IC, wherein the counters generate counter data corresponding to the transactions. The method can include capturing signals of the interface as trace data for a trace window using an integrated logic analyzer within the IC, wherein a start of the trace window begins after a start of the tracking of the transactions using the plurality of counters. The method can also include using a host data processing system coupled to the IC, determining transaction level information for the interface using the counter data and the trace data for the trace window.

公开(公告)号：US20240354478A1

公开(公告)日：2024-10-24

申请号：US18137207

申请日：2023-04-20

Applicant: Xilinx, Inc.

Inventor： Alok Mistry ,  Niloy Roy ,  Shanish Chandra Mishra ,  Anil Kumar A V

IPC: G06F30/33 ,  G06F30/327

CPC classification number: G06F30/33 ,  G06F30/327

Abstract: Disclosed methods and systems include debug circuitry registering candidate sample values in a plurality of sample periods while application circuitry is active. The candidate sample values indicate states of a plurality of candidate signals of the application circuitry. Sample values of first probed signals from each sample period are written to a sample memory using a mapping based on bit-widths of the first probed signals. The sample values of the first probed signals are selected from the candidate sample values. The mapping is updated based on bit-widths of second probed signals, and sample values of the second probed signals from each sample period are written to the sample memory using the mapping. The sample values of the second probed signals are selected from the candidate sample values.

公开(公告)号：US10161999B1

公开(公告)日：2018-12-25

申请号：US15091376

申请日：2016-04-05

Applicant: Xilinx, Inc.

Inventor： Heera Nand ,  Niloy Roy ,  Mahesh Sankroj ,  Siddharth Rele ,  Riyas Noorudeen Remla ,  Rajesh Bansal ,  Bradley K. Fross

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.

公开(公告)号：US11442844B1

公开(公告)日：2022-09-13

申请号：US16889590

申请日：2020-06-01

Applicant: Xilinx, Inc.

Inventor： Michael E. Peattie ,  Niloy Roy ,  Vishal Kumar Vangala

IPC: G06F11/00 ,  G06F11/36 ,  G06F11/27 ,  H04L49/109 ,  G01R31/3185 ,  G06F11/07

Abstract: An integrated circuit includes a high-speed interface configured to communicate with a host system for debugging and a debug hub coupled to the high-speed interface. The debug hub is configured to receive a debug command from the host system as memory mapped data. The integrated circuit also includes a plurality of debug cores coupled to the debug hub. Each debug core is coupled to the debug hub by channels. The debug hub is configured to translate the debug command to a data stream and provide the data stream to a target debug core of the plurality of debug cores based on an address specified by the debug command.

公开(公告)号：US10078113B1

公开(公告)日：2018-09-18

申请号：US14736790

申请日：2015-06-11

Applicant: Xilinx, Inc.

Inventor： Kapil Usgaonkar ,  Niloy Roy

IPC: G01R31/28 ,  G06F11/00 ,  G01R31/3177

CPC classification number: G01R31/31705 ,  G06F11/322 ,  G06F11/364

Abstract: Various example implementations are directed to circuits and methods for debugging logic circuits utilizing a data bus for communication. According to an example implementation, an apparatus includes a logic circuit configured to communicate data over a data bus according to a communication protocol. The apparatus also includes a logic analyzer circuit coupled to the data bus. The logic analyzer circuit is configured to capture, in response to a control signal, samples of data signals communicated on the data bus. The logic analyzer circuit determines respective pairs of start and end positions of the data transactions in the captured samples. The logic analyzer circuit outputs the samples of the data signals and a set of metadata including the determined pairs of start and end positions of data transactions in the samples.