公开(公告)号：US20240354478A1

公开(公告)日：2024-10-24

申请号：US18137207

申请日：2023-04-20

Applicant: Xilinx, Inc.

Inventor： Alok Mistry ,  Niloy Roy ,  Shanish Chandra Mishra ,  Anil Kumar A V

IPC: G06F30/33 ,  G06F30/327

CPC classification number: G06F30/33 ,  G06F30/327

Abstract: Disclosed methods and systems include debug circuitry registering candidate sample values in a plurality of sample periods while application circuitry is active. The candidate sample values indicate states of a plurality of candidate signals of the application circuitry. Sample values of first probed signals from each sample period are written to a sample memory using a mapping based on bit-widths of the first probed signals. The sample values of the first probed signals are selected from the candidate sample values. The mapping is updated based on bit-widths of second probed signals, and sample values of the second probed signals from each sample period are written to the sample memory using the mapping. The sample values of the second probed signals are selected from the candidate sample values.