公开(公告)号：US09065446B1

公开(公告)日：2015-06-23

申请号：US14294406

申请日：2014-06-03

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri ,  Amit Gupta ,  Fu-Hing Ho

IPC: G06F17/50 ,  H03K19/177

CPC classification number: H03K19/17792 ,  G06F17/5031 ,  G06F17/5045 ,  G06F17/5054 ,  G06F2217/84 ,  H03K19/1774

Abstract: Approaches for generating delay values for instances of a circuit include inputting possible contexts of the circuit. Each context includes a respective delay value and a combination of possible types of a plurality of characteristics of the circuit, and each characteristic is of one type of a plurality of alternative types of the characteristic. A plurality of classification parameters is input and the classification parameters indicate selected ones of the characteristics. Groups of contexts are selected based on the plurality of classification parameters. Each group includes one or more of the contexts, and each context includes the plurality of characteristics. A combination of types of the selected characteristics in each context in a group is equal to the combination of types of the selected characteristics of each other context in the group. For each group, a mean and a standard deviation of the respective delay values are determined and output.

Abstract translation: 为电路实例产生延迟值的方法包括输入电路的可能上下文。 每个上下文包括各自的延迟值和电路的多个特性的可能类型的组合，并且每个特征是特征的多种替代类型的一种类型。 输入多个分类参数，分类参数表示选定的特征。 基于多个分类参数来选择上下文组。 每个组包括上下文中的一个或多个，并且每个上下文包括多个特征。 组中每个上下文中所选特征的类型的组合等于组中每个其他上下文的所选特征的类型的组合。 对于每个组，确定并输出各个延迟值的平均值和标准偏差。

公开(公告)号：US10565346B1

公开(公告)日：2020-02-18

申请号：US15640009

申请日：2017-06-30

Applicant: Xilinx, Inc.

Inventor： Vishal Suthar ,  Dinesh D. Gaitonde ,  Amit Gupta ,  Jinny Singh

IPC: G06F17/50

Abstract: Implementing a circuit design can include generating an integer linear programming (ILP) formulation for a routing problem by determining constraints for implementing nets of a circuit design within a programmable network-on-chip (NOC) of an integrated circuit, wherein the constraints include placement constraints and routability constraints for the nets. The nets can be simultaneously placed and routed by executing an ILP solver using a processor to minimize an objective function of the ILP formulation while observing the constraints. The ILP solver maps logical units of the nets to interface circuits of the programmable NOC concurrently with mapping the nets to channels of the programmable NOC.

公开(公告)号：US11681846B1

公开(公告)日：2023-06-20

申请号：US17147163

申请日：2021-01-12

Applicant: XILINX, INC.

Inventor： Xiaojian Yang ,  Frederic Revenu ,  Dinesh D. Gaitonde ,  Amit Gupta

IPC: G06F30/343 ,  G06F30/347

CPC classification number: G06F30/343 ,  G06F30/347

Abstract: A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.

公开(公告)号：US08751997B1

公开(公告)日：2014-06-10

申请号：US13804774

申请日：2013-03-14

Applicant: Xilinx, Inc.

Inventor： Amit Gupta

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5031 ,  G06F2217/84

Abstract: Up-binning a circuit design includes receiving a first bitstream specifying the circuit design. The circuit design meets a timing requirement for a first speed grade of a programmable integrated circuit. Using a processor, a first parameter of the first bitstream is determined. The first parameter is applied to a hardware netlist of the programmable integrated circuit resulting in a parameterized hardware netlist specifying the circuit design. A timing analysis is performed upon the parameterized hardware netlist. The process further includes determining, from the timing analysis, whether at least a portion of the parameterized hardware netlist meets the timing requirement when using timing data for a second speed grade of the programmable integrated circuit. The second speed grade is slower than the first speed grade.

Abstract translation: 上行电路设计包括接收指定电路设计的第一比特流。 电路设计符合可编程集成电路第一速度等级的时序要求。 使用处理器，确定第一比特流的第一参数。 第一个参数应用于可编程集成电路的硬件网表，从而产生一个指定电路设计的参数化硬件网表。 在参数化的硬件网表上执行时序分析。 该过程还包括当使用可编程集成电路的第二速度等级的定时数据时，从定时分析确定参数化硬件网表的至少一部分是否满足定时要求。 第二速度档次比第一档次要慢。