公开(公告)号：US10318681B1

公开(公告)日：2019-06-11

申请号：US15635461

申请日：2017-06-28

Applicant: Xilinx, Inc.

Inventor： Fu-Hing Ho ,  Johnie Au

IPC: G06F17/50

Abstract: Leakage current estimation for a circuit can include generating a cell leakage library including cell-level leakage current geometry data for different states of cells of a cell library, wherein the cells are specified as transistor-level netlists, and determining, using a processor, gate-level leakage current geometry data for gates of a gate-level netlist for the circuit based upon states of the gates for a selected operating state of the circuit and the cell-level leakage current geometry data. Total leakage current geometry data can be determined, using the processor, for the gate-level netlist by aggregating the gate-level leakage current geometry data.

公开(公告)号：US20160056823A1

公开(公告)日：2016-02-25

申请号：US14466569

申请日：2014-08-22

Applicant: Xilinx, Inc.

Inventor： Fu-Hing Ho ,  Gubo Huang

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/017581 ,  H03K19/0185

Abstract: In an example implementation, a level-shifter circuit in an integrated circuit (IC) includes a plurality field-effect transistors (FETs) coupled to provide: a first inverter having an input port configured to receive an input signal having a first supply voltage, an output port, and a bias port; a second inverter having an input port coupled to the output port of the first inverter, an output port, and a bias port coupled to a second supply voltage; a diode-connected FET coupled between the second supply voltage and the bias port of the first inverter; a first FET in parallel with the diode-connected FET having a gate coupled to the output of the second inverter; and a second FET in parallel with the diode-connected FET and the first FET having a gate configured to receive a mode select signal.

Abstract translation: 在示例实现中，集成电路（IC）中的电平移动器电路包括多个场效应晶体管（FET），其耦合以提供：第一反相器，其具有被配置为接收具有第一电源电压的输入信号的输入端口， 输出端口和偏置端口; 第二反相器具有耦合到第一反相器的输出端口的输入端口，输出端口和耦合到第二电源电压的偏置端口; 耦合在第二电源电压和第一反相器的偏置端口之间的二极管连接的FET; 与二极管连接的FET并联的第一FET，具有耦合到第二反相器的输出端的栅极; 以及与二极管连接的FET并联的第二FET和具有配置为接收模式选择信号的栅极的第一FET。

公开(公告)号：US09915696B1

公开(公告)日：2018-03-13

申请号：US14792189

申请日：2015-07-06

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri ,  Fu-Hing Ho

IPC: G06F19/00 ,  G01R31/36 ,  G01R31/317 ,  G01R31/28 ,  G01R31/3183

CPC classification number: G01R31/3016 ,  G01R31/31725 ,  G01R31/318516

Abstract: Techniques for adaptively scaling power supply voltage of a programmable integrated circuit. Compact speed-testing ring oscillators are inserted into a pre-constructed circuit model to test the speed of speed-critical aspects of the interconnect fabric of the programmable integrated circuit. The speed-testing ring oscillators are compact due to including only two elements configured from lookup table elements (“LUTs”) of the programmable integrated circuit. The speed-testing ring oscillators are connected to a power management unit which receives speed values output from the speed-testing ring oscillators and adjusts the power supply voltage to maintain the speed-testing ring oscillators operating at or above a prescribed speed. If all speed-testing ring oscillators are operating too fast, then power management unit reduces voltage to reduce the total power consumed by the programmable integrated circuit while still maintaining operation above a desired speed.

公开(公告)号：US09407266B2

公开(公告)日：2016-08-02

申请号：US14466569

申请日：2014-08-22

Applicant: Xilinx, Inc.

Inventor： Fu-Hing Ho ,  Gubo Huang

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/017581 ,  H03K19/0185

Abstract: In an example implementation, a level-shifter circuit in an integrated circuit (IC) includes a plurality field-effect transistors (FETs) coupled to provide: a first inverter having an input port configured to receive an input signal having a first supply voltage, an output port, and a bias port; a second inverter having an input port coupled to the output port of the first inverter, an output port, and a bias port coupled to a second supply voltage; a diode-connected FET coupled between the second supply voltage and the bias port of the first inverter; a first FET in parallel with the diode-connected FET having a gate coupled to the output of the second inverter; and a second FET in parallel with the diode-connected FET and the first FET having a gate configured to receive a mode select signal.

Abstract translation: 在示例实现中，集成电路（IC）中的电平移动器电路包括多个场效应晶体管（FET），其耦合以提供：第一反相器，其具有被配置为接收具有第一电源电压的输入信号的输入端口， 输出端口和偏置端口; 第二反相器具有耦合到第一反相器的输出端口的输入端口，输出端口和耦合到第二电源电压的偏置端口; 耦合在第二电源电压和第一反相器的偏置端口之间的二极管连接的FET; 与二极管连接的FET并联的第一FET，具有耦合到第二反相器的输出端的栅极; 以及与二极管连接的FET并联的第二FET和具有配置为接收模式选择信号的栅极的第一FET。

公开(公告)号：US09065446B1

公开(公告)日：2015-06-23

申请号：US14294406

申请日：2014-06-03

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri ,  Amit Gupta ,  Fu-Hing Ho

IPC: G06F17/50 ,  H03K19/177

CPC classification number: H03K19/17792 ,  G06F17/5031 ,  G06F17/5045 ,  G06F17/5054 ,  G06F2217/84 ,  H03K19/1774

Abstract: Approaches for generating delay values for instances of a circuit include inputting possible contexts of the circuit. Each context includes a respective delay value and a combination of possible types of a plurality of characteristics of the circuit, and each characteristic is of one type of a plurality of alternative types of the characteristic. A plurality of classification parameters is input and the classification parameters indicate selected ones of the characteristics. Groups of contexts are selected based on the plurality of classification parameters. Each group includes one or more of the contexts, and each context includes the plurality of characteristics. A combination of types of the selected characteristics in each context in a group is equal to the combination of types of the selected characteristics of each other context in the group. For each group, a mean and a standard deviation of the respective delay values are determined and output.

Abstract translation: 为电路实例产生延迟值的方法包括输入电路的可能上下文。 每个上下文包括各自的延迟值和电路的多个特性的可能类型的组合，并且每个特征是特征的多种替代类型的一种类型。 输入多个分类参数，分类参数表示选定的特征。 基于多个分类参数来选择上下文组。 每个组包括上下文中的一个或多个，并且每个上下文包括多个特征。 组中每个上下文中所选特征的类型的组合等于组中每个其他上下文的所选特征的类型的组合。 对于每个组，确定并输出各个延迟值的平均值和标准偏差。