公开(公告)号：US20250147799A1

公开(公告)日：2025-05-08

申请号：US18501868

申请日：2023-11-03

Applicant: Xilinx, Inc.

Inventor： Thomas Calvert ,  Ripduman Sohan ,  Dmitri Kitariev ,  Kimon Karras ,  Stephan Diestelhorst ,  Neil Turton ,  David Riddoch ,  Derek Roberts ,  Kieran Mansley ,  Steven Pope

IPC: G06F9/48

Abstract: A computer-implemented method for task management can include managing performance of a task on a message by a plurality of circuits. In some aspects, the task can comprise a sequence of processings to be performed on the message and each circuit of the plurality of circuits performing a processing of the sequence of processings. In some aspects, the method can include routing, based on the sequence, a first information regarding the task to a first circuit of the plurality of circuits to perform a first processing of the sequence of processings on the message; receiving, from the first circuit, an output of the first processing; and routing, based on the sequence of processings identified for the task, a second information regarding the task to a second circuit of the plurality of circuits to perform a second processing that follows the first processing in the sequence of processings.

公开(公告)号：US20250112933A1

公开(公告)日：2025-04-03

申请号：US18478438

申请日：2023-09-29

Applicant: Xilinx, Inc.

Inventor： David Andrews ,  David Lawrie ,  Victor Wu ,  Po-Ching Sun ,  Dmitri Kitariev ,  David Riddoch

IPC: H04L9/40 ,  H04L1/00 ,  H04L43/0823

Abstract: Described herein are systems and methods for managing error detection in a message. A circuit can identify, based on an error detection configuration of the at least one circuit, a first portion of the message to be checked for errors before a second portion of the message is available to the at least one circuit, the first portion being less than all of the message to be checked for one or more errors. A circuit can analyze a number of bits of the first portion of the message using the at least one circuit and based on the error detection configuration. A circuit can, based on analyzing the first portion, determine whether the message includes the one or more errors. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250007684A1

公开(公告)日：2025-01-02

申请号：US18345792

申请日：2023-06-30

Applicant: Xilinx, Inc.

Inventor： Mark Richard Nethercot ,  Martin Rhodes ,  David Riddoch ,  Connor Hughes ,  Gareth David Edwards

IPC: H04L7/00

Abstract: A computer-implemented method for managing channel accessibility can include detecting, by a first circuit, a transmit request from the first circuit to transmit a message into a communication channel connecting the first circuit to second circuit. The method can include determining, by the first circuit, whether to approve the transmit request based on an evaluation of a first number associated with messages previously transmitted by the first circuit to the second circuit over the communication channel and a second number associated with processing by the second circuit of the messages previously transmitted by the first circuit. The method can include, in response to determining to approve the transmit request, transmitting, by the first circuit, the message into the communication channel. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250004782A1

公开(公告)日：2025-01-02

申请号：US18345994

申请日：2023-06-30

Applicant: Xilinx, Inc.

Inventor： Mark Richard Nethercot ,  Martin Rhodes ,  Ricardo Gonzalez Toral ,  Colin Stirling ,  Dmitri Kitariev ,  David Riddoch

IPC: G06F9/38

Abstract: A computer-implemented method for managing processing order for a plurality of commands can include in response to receiving each command of a plurality of commands in a receipt order, assigning each respective command of the plurality of commands to a respective processing queue of a plurality of processing queues to be processed, and setting, for each of the plurality of commands and in the receipt order, an identifier based on the respective queue assigned to each of the plurality of commands, and managing, based on the identifiers for each of the plurality of commands in the receipt order, an order of processing of each of the plurality of commands from the respective processing queue of the plurality of processing queues. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250004941A1

公开(公告)日：2025-01-02

申请号：US18346017

申请日：2023-06-30

Applicant: Xilinx, Inc.

Inventor： Duncan Andrew Cockburn ,  David James Fraser ,  Inaki Ormaetxea ,  Gareth David Edwards ,  Dmitri Kitariev ,  David Riddoch ,  Victor Wu

IPC: G06F12/02

Abstract: A computer-implemented method for memory management can include identifying a set of one or more memory blocks of virtual memory to be allocated for storage of a content into a plurality of memory banks that subdivide physical memory. The method can include storing the content in the set of one or more memory blocks of virtual memory. The method can include assigning an identifier to the set of one or more memory blocks of virtual memory that store the content. The method can include outputting the identifier for the set of one or more memory blocks of virtual memory. Various other methods, systems, and computer-readable media are also disclosed.