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公开(公告)号:US11824830B2
公开(公告)日:2023-11-21
申请号:US17246310
申请日:2021-04-30
Applicant: Xilinx, Inc.
Inventor: Steven Leslie Pope , Neil Turton , David James Riddoch , Dmitri Kitariev , Ripduman Sohan , Derek Edward Roberts
CPC classification number: H04L63/0227 , H04L63/029
Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.
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公开(公告)号:US20220027273A1
公开(公告)日:2022-01-27
申请号:US17493694
申请日:2021-10-04
Applicant: Xilinx, Inc.
Inventor: Steven L. Pope , Dmitri Kitariev , David J. Riddoch , Derek Roberts , Neil Turton
IPC: G06F12/0831 , G06F9/38 , G06F12/0888 , G06F13/28
Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.
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公开(公告)号:US11138116B2
公开(公告)日:2021-10-05
申请号:US16525313
申请日:2019-07-29
Applicant: XILINX, INC.
Inventor: Steven L. Pope , Dmitri Kitariev , David J. Riddoch , Derek Roberts , Neil Turton
IPC: G06F12/0831 , G06F9/38 , G06F12/0888 , G06F13/28 , G06F13/38 , G06F13/42 , G06F13/12
Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.
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公开(公告)号:US11082364B2
公开(公告)日:2021-08-03
申请号:US16395027
申请日:2019-04-25
Applicant: Xilinx, Inc.
Inventor: Steven Leslie Pope , Neil Turton , David James Riddoch , Dmitri Kitariev , Ripduman Sohan , Derek Edward Roberts
IPC: H04L12/947 , H04L29/06 , G06F9/24 , G06F9/28 , G06F9/30 , G06F8/41 , H03K19/177
Abstract: A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.
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公开(公告)号:US20210258284A1
公开(公告)日:2021-08-19
申请号:US17246310
申请日:2021-04-30
Applicant: Xilinx, Inc.
Inventor: Steven Leslie Pope , Neil Turton , David James Riddoch , Dmitri Kitariev , Ripduman Sohan , Derek Edward Roberts
IPC: H04L29/06
Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.
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公开(公告)号:US11012411B2
公开(公告)日:2021-05-18
申请号:US16180883
申请日:2018-11-05
Applicant: Xilinx, Inc.
Inventor: Steven Leslie Pope , Neil Turton , David James Riddoch , Dmitri Kitariev , Ripduman Sohan , Derek Edward Roberts
IPC: H04L29/06
Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.
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公开(公告)号:US11693777B2
公开(公告)日:2023-07-04
申请号:US17493694
申请日:2021-10-04
Applicant: Xilinx, Inc.
Inventor: Steven L. Pope , Dmitri Kitariev , David J. Riddoch , Derek Roberts , Neil Turton
IPC: G06F12/0831 , G06F9/38 , G06F12/0888 , G06F13/28
CPC classification number: G06F12/0835 , G06F9/3802 , G06F12/0888 , G06F13/28
Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.
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公开(公告)号:US20250147799A1
公开(公告)日:2025-05-08
申请号:US18501868
申请日:2023-11-03
Applicant: Xilinx, Inc.
Inventor: Thomas Calvert , Ripduman Sohan , Dmitri Kitariev , Kimon Karras , Stephan Diestelhorst , Neil Turton , David Riddoch , Derek Roberts , Kieran Mansley , Steven Pope
IPC: G06F9/48
Abstract: A computer-implemented method for task management can include managing performance of a task on a message by a plurality of circuits. In some aspects, the task can comprise a sequence of processings to be performed on the message and each circuit of the plurality of circuits performing a processing of the sequence of processings. In some aspects, the method can include routing, based on the sequence, a first information regarding the task to a first circuit of the plurality of circuits to perform a first processing of the sequence of processings on the message; receiving, from the first circuit, an output of the first processing; and routing, based on the sequence of processings identified for the task, a second information regarding the task to a second circuit of the plurality of circuits to perform a second processing that follows the first processing in the sequence of processings.
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公开(公告)号:US10742782B2
公开(公告)日:2020-08-11
申请号:US15607221
申请日:2017-05-26
Applicant: XILINX, INC.
Inventor: Steven L. Pope , Derek Roberts , Neil Turton
Abstract: A network interface device is provided. The network interface device comprises an input configured to receive a data frame from a network. The network interface device also comprises a timing component configured to store, for the data frame, first timing information and compensation information. The compensation information is specific to the frame. The first timing information and said compensation information representing a time when the data frame was received.
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