公开(公告)号：US11543452B1

公开(公告)日：2023-01-03

申请号：US17014128

申请日：2020-09-08

Applicant: Xilinx, Inc.

Inventor： Saikat Bandyopadhyay ,  Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Ender Tunc Eroglu ,  Rupendra Bakoliya ,  Jayashree Rangarajan

IPC: G06F11/00 ,  G01R31/3183 ,  G06F30/3308

Abstract: A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the subset of leaf nodes is generated. The bypass module is generated in response to detecting presence of the subset of leaf nodes in the electronic design with input/output signaling of more than two values. The bypass module facilitates communication between the testbench and the subset of leaf nodes. Leaf nodes other than the subset of leaf nodes communicate with the testbench without communicating through the bypass module.

公开(公告)号：US20230252212A1

公开(公告)日：2023-08-10

申请号：US17650035

申请日：2022-02-04

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Saikat Bandyopadhyay ,  Ashish Kumar Jain ,  Shiyao Ge ,  Tapodyuti Mandal ,  Miti Joshi

IPC: G06F30/333 ,  G06F30/3308 ,  G06F30/327

CPC classification number: G06F30/333 ,  G06F30/3308 ,  G06F30/327

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.

公开(公告)号：US12271670B2

公开(公告)日：2025-04-08

申请号：US17650035

申请日：2022-02-04

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Saikat Bandyopadhyay ,  Ashish Kumar Jain ,  Shiyao Ge ,  Tapodyuti Mandal ,  Miti Joshi

IPC: G06F30/333 ,  G06F30/327 ,  G06F30/3308

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.