公开(公告)号：US10671785B1

公开(公告)日：2020-06-02

申请号：US15370339

申请日：2016-12-06

Applicant: Xilinx, Inc.

Inventor： Valeria Mihalache ,  Kumar Deepak ,  Saikat Bandyopadhyay ,  Sandeep S. Deshpande ,  Feng Cai

IPC: G06F30/367

Abstract: Simulating a hardware description language design including a core and a testbench can include performing, using a processor, a first compilation of the hardware description language design by generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data describing signals crossing a compile checkpoint boundary. A subsequent compilation of the hardware description language design can be performed by reusing the compiled core unit from the first compilation and generating a new compiled testbench for the testbench using the synchronization data.

公开(公告)号：US20240012973A1

公开(公告)日：2024-01-11

申请号：US17862061

申请日：2022-07-11

Applicant: Xilinx, Inc.

Inventor： Sandeep S. Deshpande ,  Saikat Bandyopadhyay

IPC: G06F30/367

CPC classification number: G06F30/367

Abstract: Simulation of a waveform in a circuit simulation includes preparing, in response to a programming interface call by a testbench, a schedule of states of a signal at two or more intervals in the simulation by a simulator. The programming interface call specifies a sequence of the states and indicates durations of the states during the simulation. The signal is set to a first state of the sequence by the simulator during the simulation and then to a second state of the sequence according to the schedule.

公开(公告)号：US11543452B1

公开(公告)日：2023-01-03

申请号：US17014128

申请日：2020-09-08

Applicant: Xilinx, Inc.

Inventor： Saikat Bandyopadhyay ,  Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Ender Tunc Eroglu ,  Rupendra Bakoliya ,  Jayashree Rangarajan

IPC: G06F11/00 ,  G01R31/3183 ,  G06F30/3308

Abstract: A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the subset of leaf nodes is generated. The bypass module is generated in response to detecting presence of the subset of leaf nodes in the electronic design with input/output signaling of more than two values. The bypass module facilitates communication between the testbench and the subset of leaf nodes. Leaf nodes other than the subset of leaf nodes communicate with the testbench without communicating through the bypass module.

公开(公告)号：US11003818B1

公开(公告)日：2021-05-11

申请号：US16790578

申请日：2020-02-13

Applicant: Xilinx, Inc.

Inventor： Ashish Kumar Jain ,  Saikat Bandyopadhyay ,  Jason Villarreal

IPC: G06F30/00 ,  G06F30/33 ,  G06F9/30 ,  G06F30/3308 ,  G06F7/499

Abstract: A method includes parsing and compiling a software code that includes a constraint bitwise operation with a first operand associated with a first constraint range and a second operand associated with a second constraint range. A first and a second plurality of ranges that spans the first and second constraint range are generated. In some embodiments, each constrained range is converted into a binary format having an upper bit portion and a lower bit portion. The upper bit portion for the each range remains unchanged. A resultant range associated with the constraint bitwise operation is determined based on performing the constraint bitwise operation on the first and the second plurality of ranges.

公开(公告)号：US10726182B1

公开(公告)日：2020-07-28

申请号：US16100041

申请日：2018-08-09

Applicant: Xilinx, Inc.

Inventor： Sandeep S. Deshpande ,  Feng Cai ,  Saikat Bandyopadhyay

IPC: G06F17/50 ,  G06F30/3312 ,  G06F9/448 ,  G06F30/327

Abstract: Disclosed approaches involve simulating a circuit design specified in a hardware description language (HDL). During simulation, a thread is started at an edge of a simulation clock signal for evaluation of states of a finite state machine (FSM) that represent a series of events specified in a statement in the HDL. The thread transitions from one state to a next state in the FSM in response to evaluation of the one state. In response to encountering a fork state in the FSM, the thread is forked into two threads during simulation. The fork state represents a composite operator in the statement, and the FSM has a branch from the fork state for each operand of the composite operator. In response to encountering a join state in the FSM by the two threads, the two threads are joined into one thread.

公开(公告)号：US12271670B2

公开(公告)日：2025-04-08

申请号：US17650035

申请日：2022-02-04

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Saikat Bandyopadhyay ,  Ashish Kumar Jain ,  Shiyao Ge ,  Tapodyuti Mandal ,  Miti Joshi

IPC: G06F30/333 ,  G06F30/327 ,  G06F30/3308

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.

公开(公告)号：US20240232482A9

公开(公告)日：2024-07-11

申请号：US18049585

申请日：2022-10-25

Applicant: Xilinx, Inc.

Inventor： Saikat Bandyopadhyay ,  Rajvinder S. Klair

IPC: G06F30/31

CPC classification number: G06F30/31 ,  G06F2111/20

Abstract: An adaptable framework for circuit design simulation verification generates a simulation database for a circuit design and processed design data for the circuit design. The processed design data includes source files for the circuit design referenced by the simulation database. The simulation database and the processed design data are exported from a host integrated development environment (IDE). A template writer configured to generate a simulation script for the circuit design using the simulation database is provided. The simulation script is generated by executing the template writer. The simulation script is generated according to one or more user-specified parameters of the template writer using the simulation database and the processed design data as exported.

公开(公告)号：US20240135074A1

公开(公告)日：2024-04-25

申请号：US18049585

申请日：2022-10-24

Applicant: Xilinx, Inc.

Inventor： Saikat Bandyopadhyay ,  Rajvinder S. Klair

IPC: G06F30/31

CPC classification number: G06F30/31 ,  G06F2111/20

Abstract: An adaptable framework for circuit design simulation verification generates a simulation database for a circuit design and processed design data for the circuit design. The processed design data includes source files for the circuit design referenced by the simulation database. The simulation database and the processed design data are exported from a host integrated development environment (IDE). A template writer configured to generate a simulation script for the circuit design using the simulation database is provided. The simulation script is generated by executing the template writer. The simulation script is generated according to one or more user-specified parameters of the template writer using the simulation database and the processed design data as exported.

公开(公告)号：US11443088B1

公开(公告)日：2022-09-13

申请号：US16897899

申请日：2020-06-10

Applicant: Xilinx, Inc.

Inventor： Gaurav Kumar Verma ,  Saikat Bandyopadhyay

IPC: G06F11/26 ,  G06F9/44 ,  G06F30/331 ,  G06F16/901 ,  G06F9/30 ,  G06F9/46 ,  G06F16/22 ,  G06F16/955 ,  G06F16/23 ,  G06F16/9535 ,  G06F16/951 ,  G06F9/4401 ,  G06F16/28 ,  G06F9/54

Abstract: Simulation of a circuit design using accelerated models can include determining, using computer hardware, that a design unit of a circuit design specified in a hardware description language is a prime block and determining, using the computer hardware, an output vector corresponding to an output of the prime block. Using the computer hardware, contents of the prime block can be replaced with an accelerated simulation model specified in a high level language, wherein the accelerated simulation model can determine a value for the output of the prime block as a function of values of one or more inputs of the prime block using the output vector. Using the computer hardware, the circuit design can be elaborated and compiled into object code that is executable to simulate the circuit design.

公开(公告)号：US20230252212A1

公开(公告)日：2023-08-10

申请号：US17650035

申请日：2022-02-04

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Saikat Bandyopadhyay ,  Ashish Kumar Jain ,  Shiyao Ge ,  Tapodyuti Mandal ,  Miti Joshi

IPC: G06F30/333 ,  G06F30/3308 ,  G06F30/327

CPC classification number: G06F30/333 ,  G06F30/3308 ,  G06F30/327

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.