公开(公告)号：US20230252212A1

公开(公告)日：2023-08-10

申请号：US17650035

申请日：2022-02-04

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Saikat Bandyopadhyay ,  Ashish Kumar Jain ,  Shiyao Ge ,  Tapodyuti Mandal ,  Miti Joshi

IPC: G06F30/333 ,  G06F30/3308 ,  G06F30/327

CPC classification number: G06F30/333 ,  G06F30/3308 ,  G06F30/327

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.

公开(公告)号：US12271670B2

公开(公告)日：2025-04-08

申请号：US17650035

申请日：2022-02-04

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Saikat Bandyopadhyay ,  Ashish Kumar Jain ,  Shiyao Ge ,  Tapodyuti Mandal ,  Miti Joshi

IPC: G06F30/333 ,  G06F30/327 ,  G06F30/3308

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.