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    Dynamic scan chain reconfiguration in an integrated circuit
    1.
    发明授权
    Dynamic scan chain reconfiguration in an integrated circuit 有权

    公开(公告)号：US10317464B2

    公开(公告)日：2019-06-11

    申请号：US15589644

    申请日：2017-05-08

    Applicant: Xilinx, Inc.

    Inventor： Partho Tapan Chaudhuri

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/267 ,  G06F11/27

    Abstract: An example test circuit for an integrated circuit (IC) having a plurality of scan chains includes: a first circuit and a second circuit; and a scan chain router coupled between the first circuit and the plurality of scan chains and coupled between the second circuit and the plurality of scan chains, the scan chain router responsive to an enable signal to: (1) couple the first circuit to each of the plurality of scan chains; or (2) couple the second circuit to one or more concatenated scan chains, where each concatenated scan chain includes a concatenation of two or more of the plurality of scan chains.

    Circuit architecture for expanded design for testability functionality
    2.
    发明授权
    Circuit architecture for expanded design for testability functionality 有权

    公开(公告)号：US11263377B1

    公开(公告)日：2022-03-01

    申请号：US17219174

    申请日：2021-03-31

    Applicant: Xilinx, Inc.

    Inventor： Amitava Majumdar ,  Albert Shih-Huai Lin ,  Partho Tapan Chaudhuri ,  Niravkumar Patel

    IPC: G06F30/333 ,  G06F30/3308 ,  G06F30/398 ,  G06F11/00 ,  G01R31/28 ,  H01L25/00 ,  H03K19/00 ,  G06F115/08 ,  G06F11/08

    Abstract: A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing interface configured to connect to circuitry outside of the circuit block and an inward facing interface configured to connect to circuitry within the circuit block. The instance of the IP core can be parameterized to configure the infrastructure harness circuit to control a plurality of functions selected from the expanded design for testability functions based on a user parameterization of the instance of the IP core.

    Scalable scan architecture for multi-circuit block arrays
    3.
    发明授权
    Scalable scan architecture for multi-circuit block arrays 有权

    公开(公告)号：US11639962B1

    公开(公告)日：2023-05-02

    申请号：US17199874

    申请日：2021-03-12

    Applicant: Xilinx, Inc.

    Inventor： Niravkumar Patel ,  Amitava Majumdar ,  Partho Tapan Chaudhuri

    IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/27

    Abstract: An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.

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