公开(公告)号：US10013517B1

公开(公告)日：2018-07-03

申请号：US14989683

申请日：2016-01-06

Applicant: Xilinx, Inc.

Inventor： Sheng Zhou ,  Bin Ochotta ,  Alec J. Wong ,  Pradip K. Jha ,  Qin Zhang

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/66

Abstract: High level synthesis for a circuit design may include detecting, using a processor, an encrypted, high level programming language (HLL) core for inclusion in a circuit design, decrypting, using the processor, the encrypted HLL core into volatile memory, and generating, using the processor, an encrypted, intermediate representation (IR) of the circuit design including an encrypted IR of the HLL core. An encrypted hardware description language (HDL) circuit design may be generated, using the processor, from the encrypted IR of the circuit design. The encrypted HDL circuit design includes an encrypted HDL core that is functionally equivalent to the encrypted HLL core.