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    System and method for import and export of design constraints
    1.
    发明授权
    System and method for import and export of design constraints 有权
    导入和导出设计约束的系统和方法

    公开(公告)号：US08612916B1

    公开(公告)日：2013-12-17

    申请号：US13709733

    申请日：2012-12-10

    Applicant: Xilinx, Inc.

    Inventor： Brendan M. O'Higgins ,  Pradip K. Jha ,  Dinesh K. Monga ,  David A. Knol

    IPC: G06F17/50

    CPC classification number: G06F17/5054

    Abstract: A method is provided for exporting design constraints from a circuit design. In response to a first user command indicating a design constraint and a pattern, the design constraint is assigned to each object in the circuit design that matches the pattern, and the pattern is stored in a database. In response to a second user command to export design constraints of the circuit design, for each design constraint assigned to a respective set of objects of the circuit design, a pattern stored in the database that matches the respective set of the objects is determined and the design constraint is added to an export file in a format that uses the determined pattern. Design constraints on individual ones of the set of the objects indicated by the determined pattern are omitted from the export file.

    Abstract translation: 提供了一种从电路设计中输出设计约束的方法。 响应于指示设计约束和模式的第一用户命令，将设计约束分配给与模式匹配的电路设计中的每个对象，并且将模式存储在数据库中。 响应于第二用户命令导出电路设计的设计约束，对于分配给电路设计的相应对象集合的每个设计约束，确定存储在数据库中与对象的相应集合匹配的模式，并且 设计约束以使用确定的模式的格式添加到导出文件。 导出文件中省略了由确定的图案指示的对象集中的各个对象的设计约束。

    High level programming language core protection for high level synthesis
    2.
    发明授权
    High level programming language core protection for high level synthesis 有权

    公开(公告)号：US10013517B1

    公开(公告)日：2018-07-03

    申请号：US14989683

    申请日：2016-01-06

    Applicant: Xilinx, Inc.

    Inventor： Sheng Zhou ,  Bin Ochotta ,  Alec J. Wong ,  Pradip K. Jha ,  Qin Zhang

    IPC: G06F17/00 ,  G06F17/50

    CPC classification number: G06F17/505 ,  G06F2217/66

    Abstract: High level synthesis for a circuit design may include detecting, using a processor, an encrypted, high level programming language (HLL) core for inclusion in a circuit design, decrypting, using the processor, the encrypted HLL core into volatile memory, and generating, using the processor, an encrypted, intermediate representation (IR) of the circuit design including an encrypted IR of the HLL core. An encrypted hardware description language (HDL) circuit design may be generated, using the processor, from the encrypted IR of the circuit design. The encrypted HDL circuit design includes an encrypted HDL core that is functionally equivalent to the encrypted HLL core.

    Message filtering for electronic design automation systems
    3.
    发明授权
    Message filtering for electronic design automation systems 有权

    公开(公告)号：US09824170B1

    公开(公告)日：2017-11-21

    申请号：US14989676

    申请日：2016-01-06

    Applicant: Xilinx, Inc.

    Inventor： Alec J. Wong ,  Pradip K. Jha ,  Steven Banks ,  Sudipto Chakraborty ,  Dennis McCrohan

    IPC: G06F17/00 ,  G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5068

    Abstract: Message filtering may include, during a first processing phase of a design specified in source code, creating a filter table including message filters and storing the filter table in a memory using a processor. Each message filter may specify a message criterion and an object identifier of the design. During a subsequent processing phase of the design, received messages may be compared with the message filters of the filter table using the processor. Responsive to determining that a selected message matches a message criterion and an object identifier of a selected message filter, the message may be suppressed using the processor.

    Method and apparatus for placement and routing of circuit designs
    5.
    发明授权
    Method and apparatus for placement and routing of circuit designs 有权

    公开(公告)号：US09864830B1

    公开(公告)日：2018-01-09

    申请号：US15040814

    申请日：2016-02-10

    Applicant: Xilinx, Inc.

    Inventor： Pradip K. Jha ,  Atul Srinivasan ,  Steven Banks ,  Nicholas A. Mezei

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077

    Abstract: Methods and systems are disclosed for placement and routing of a circuit design. A set of timing constraints is retrieved that specifies timing for objects included in a first shell circuit design configured to provide an interface for communication between the circuit design and the set of dedicated hardware resources on an IC. One or more objects of the first shell circuit design that do not affect timing of the circuit design are identified and removed from the first shell circuit design to produce a second shell circuit design. The circuit design is placed and routed according to timing constraints specified for objects of the first shell circuit design that are included in the second shell circuit design. The placed and routed circuit design is stored in a memory circuit.

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