公开(公告)号：US09846660B2

公开(公告)日：2017-12-19

申请号：US14539985

申请日：2014-11-12

Applicant: Xilinx, Inc.

Inventor： Henry E. Styles ,  Jeffrey M. Fifield ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Sonal Santan ,  Devadas Varma ,  Fernando J. Martinez Vallina ,  Sheng Zhou ,  Charles Kwok-Wah Lo

IPC: G06F13/12 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1689 ,  G06F13/28

Abstract: An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

公开(公告)号：US09218443B1

公开(公告)日：2015-12-22

申请号：US14539975

申请日：2014-11-12

Applicant: Xilinx, Inc.

Inventor： Henry E. Styles ,  Jeffrey M. Fifield ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Sonal Santan ,  Devadas Varma ,  Fernando J. Martinez Vallina ,  Sheng Zhou ,  Charles Kwah-Wah Lo

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F8/451

Abstract: OpenCL program compilation may include generating, using a processor, a register transfer level (RTL) description of a first kernel of a heterogeneous, multiprocessor design and integrating the RTL description of the first kernel with a base platform circuit design. The base platform circuit design provides a static interface within a programmable integrated circuit to a host of the heterogeneous, multiprocessor design. A first configuration bitstream may be generated from the RTL description of the first kernel using the processor. The first configuration bitstream specifies a hardware implementation of the first kernel and supporting data for the configuration bitstream. The first configuration bitstream and the supporting data may be included within a binary container.

Abstract translation: OpenCL程序编译可以包括使用处理器来生成异构多处理器设计的第一内核的寄存器传送级（RTL）描述，并将第一内核的RTL描述与基本平台电路设计集成。 基础平台电路设计为可编程集成电路内的静态接口提供了异构多处理器设计的主机。 可以使用处理器从第一内核的RTL描述生成第一配置比特流。 第一配置比特流指定第一内核的硬件实现和配置比特流的支持数据。 第一配置比特流和支持数据可以包括在二进制容器内。

公开(公告)号：US10013517B1

公开(公告)日：2018-07-03

申请号：US14989683

申请日：2016-01-06

Applicant: Xilinx, Inc.

Inventor： Sheng Zhou ,  Bin Ochotta ,  Alec J. Wong ,  Pradip K. Jha ,  Qin Zhang

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/66

Abstract: High level synthesis for a circuit design may include detecting, using a processor, an encrypted, high level programming language (HLL) core for inclusion in a circuit design, decrypting, using the processor, the encrypted HLL core into volatile memory, and generating, using the processor, an encrypted, intermediate representation (IR) of the circuit design including an encrypted IR of the HLL core. An encrypted hardware description language (HDL) circuit design may be generated, using the processor, from the encrypted IR of the circuit design. The encrypted HDL circuit design includes an encrypted HDL core that is functionally equivalent to the encrypted HLL core.

公开(公告)号：US20160132441A1

公开(公告)日：2016-05-12

申请号：US14539985

申请日：2014-11-12

Applicant: Xilinx, Inc.

Inventor： Henry E. Styles ,  Jeffrey M. Fifield ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Sonal Santan ,  Devadas Varma ,  Fernando J. Martinez Vallina ,  Sheng Zhou ,  Charles Kwok-Wah Lo

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1689 ,  G06F13/28

Abstract: An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

Abstract translation: 集成电路（IC）包括静态的第一区域，并且在IC和主机处理器之间提供接口。 第一区域包括具有第一主接口的第一互连电路块和具有第一从接口的第二互连电路块。 IC包括耦合到第一区域的第二区域。 第二区域实现异构多处理器设计的内核，并且包括耦合到第一互连电路块的第一主接口并被配置为从主处理器接收命令的从接口。 第二区域还包括耦合第二互连电路块的第一从接口的主接口，其中第二区域的主接口是用于存储器控制器的主站。

公开(公告)号：US10031732B1

公开(公告)日：2018-07-24

申请号：US15226768

申请日：2016-08-02

Applicant: Xilinx, Inc.

Inventor： Dong Li ,  Sheng Zhou ,  Stephen A. Neuendorffer

IPC: G06F8/41 ,  G06F8/70

Abstract: High level synthesis can include detecting, using a processor, an enumerated operation within an instruction of a loop construct of an application, determining, using the processor, whether the loop construct meets a modification condition, and responsive to determining that the loop construct meets the modification condition, modifying, using the processor, the loop construct to calculate the enumerated operation as a compile time constant, wherein the modified loop construct is functionally equivalent to the loop construct.