公开(公告)号：US11042610B1

公开(公告)日：2021-06-22

申请号：US15724942

申请日：2017-10-04

Applicant: Xilinx, Inc.

Inventor： Hem C. Neema ,  Sonal Santan ,  Bin Ochotta

IPC: G06F21/00 ,  G06F21/12 ,  H04L9/32 ,  G06F21/77 ,  H04L29/06 ,  H04W12/06 ,  H04W12/10

Abstract: Embodiments herein describe techniques for validating binary files used to configure a hardware card in a computing system. In one embodiment, the hardware card (e.g., an FPGA) includes programmable logic which the binary file can configure to perform a specialized function. In one embodiment, multiple users can configure the hardware card to perform their specialized tasks. For example, the computing system may be server on the cloud that hosts multiple VMs or a shared workstation. Permitting multiple users to directly configure and use the hardware card may present a security risk. To mitigate this risk, the embodiments herein describe techniques for validating encrypted binary files.

公开(公告)号：US10013517B1

公开(公告)日：2018-07-03

申请号：US14989683

申请日：2016-01-06

Applicant: Xilinx, Inc.

Inventor： Sheng Zhou ,  Bin Ochotta ,  Alec J. Wong ,  Pradip K. Jha ,  Qin Zhang

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/66

Abstract: High level synthesis for a circuit design may include detecting, using a processor, an encrypted, high level programming language (HLL) core for inclusion in a circuit design, decrypting, using the processor, the encrypted HLL core into volatile memory, and generating, using the processor, an encrypted, intermediate representation (IR) of the circuit design including an encrypted IR of the HLL core. An encrypted hardware description language (HDL) circuit design may be generated, using the processor, from the encrypted IR of the circuit design. The encrypted HDL circuit design includes an encrypted HDL core that is functionally equivalent to the encrypted HLL core.

公开(公告)号：US11232219B1

公开(公告)日：2022-01-25

申请号：US16264101

申请日：2019-01-31

Applicant: Xilinx, Inc.

Inventor： Bin Ochotta ,  Alec J. Wong ,  Nghia Do ,  Dennis McCrohan ,  David A. Knol ,  Premduth Vidyanandan ,  Satyam Jani

IPC: G06F21/62 ,  H04L9/08 ,  G06F21/10 ,  G06F21/76 ,  H04L9/32 ,  G06F21/60 ,  H04L9/14 ,  G06F21/64 ,  G06F21/12

Abstract: Removing protections on a session-key protected design include receiving a double encrypted vendor private key and an encrypted session key. The double encrypted vendor private key is decrypted into a single encrypted vendor-private key using a user private key, and the single encrypted vendor-private key is decrypted into a vendor private key using a vendor pass phrase. The encrypted session key is decrypted into a session key using the vendor private key, and the session-key protected design is decrypted into a plain design using the session key.