公开(公告)号：US11488887B1

公开(公告)日：2022-11-01

申请号：US16810473

申请日：2020-03-05

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Boon Y. Ang ,  Toshiyuki Hisamura ,  Suresh Parameswaran ,  Scott McCann ,  Hoa Lap Do

IPC: H01L23/367 ,  H01L21/306 ,  H01L23/00 ,  H01L23/373

Abstract: In one example, a method includes providing a first side of a semiconductor substrate with a plurality of transistors, etching a second side of the substrate, opposite the first side, with a pattern of trenches, the trenches having a pre-defined depth and width, and providing the etched semiconductor substrate in a package. In one example, the predefined depth and width of the trenches is such so as to increase the surface area of the second side of the substrate by at least 20 percent. In one example, the method also includes providing a layer of a thermal interface material (TIM) on the second side of the substrate, including to fill at least a portion of the trenches.

公开(公告)号：US09915869B1

公开(公告)日：2018-03-13

申请号：US14321591

申请日：2014-07-01

Applicant: Xilinx, Inc.

Inventor： Toshiyuki Hisamura

IPC: G06F17/00 ,  G03F7/00

CPC classification number: G03F1/00 ,  G03F1/50

Abstract: A method for fabricating an interposer wafer includes providing at least one mask having printing regions for forming a plurality of interposer designs; selecting an interposer design; and forming the interposer design on a substrate using a plurality of lithographic imaging steps. For each lithographic imaging step, at least one portion of the interposer design is printed by exposing at least one of the printing regions while blocking at least one other of the printing regions.

公开(公告)号：US20140205934A1

公开(公告)日：2014-07-24

申请号：US13746017

申请日：2013-01-21

Applicant: Xilinx, Inc.

Inventor： Toshiyuki Hisamura ,  Michael J. Hart

IPC: G03F7/20 ,  G03F1/00

CPC classification number: G03F7/2022 ,  G03F1/00 ,  G03F1/50 ,  G03F7/70466

Abstract: A reticle for multiple patterning a layer of an integrated circuit die includes a first portion with a first layout pattern for multiple patterning the layer of the integrated circuit die, and a second portion with a second layout pattern for multiple patterning the layer of the integrated circuit die. The first layout pattern is different from the second layout pattern.

Abstract translation: 用于多层图案化集成电路管芯层的掩模版包括具有第一布局图案的第一部分，用于对集成电路管芯的层进行多个图案化，以及具有第二布局图案的第二部分，用于对集成电路的层进行多个图案化 死。 第一布局模式与第二布局模式不同。