公开(公告)号：US12060635B2

公开(公告)日：2024-08-13

申请号：US16881787

申请日：2020-05-22

Applicant: Tokyo Electron Limited

Inventor： Tsuyoshi Moriya ,  Tadahiro Ishizaka ,  Yoshinori Morisada

IPC: B32B9/00 ,  C23C16/27 ,  C23C16/455 ,  G03F1/00 ,  H01L21/311

CPC classification number: C23C16/27 ,  C23C16/45536 ,  G03F1/00 ,  H01L21/31144

Abstract: In a hard mask formed on a target film formed on a substrate, a first film having a stress in a first direction and a second film having a stress in a second direction opposite to the first direction are alternately stacked one or more times.

公开(公告)号：US11841615B2

公开(公告)日：2023-12-12

申请号：US16883428

申请日：2020-05-26

Applicant: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shouqiang Zhang ,  Wenlin Mei ,  Zhuo Xu ,  Pengcheng Fu ,  Zhifu Dong

IPC: G03F1/36 ,  G03F7/00 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  G03F1/00 ,  H10K50/86 ,  H10K59/122 ,  H10K71/20

CPC classification number: G03F1/36 ,  G03F1/00 ,  G03F7/0007 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H10K50/865 ,  H10K59/122 ,  H10K71/233

Abstract: A mask includes a first light-transmitting portion. The first light-transmitting portion includes a target region and at least one compensation region connected to the target region. A planar pattern of the target region includes a plurality of corners, and a planar pattern of each compensation region extends from one of the plurality of corners. An area of the planar pattern of each compensation region is less than an area of the planar pattern of the target region.

公开(公告)号：US20230268285A1

公开(公告)日：2023-08-24

申请号：US18310743

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing, Ltd.

Inventor： Chih-Chia Hu ,  Chang-Ching Yu ,  Ming-Fa Chen

IPC: H01L23/544 ,  H01L21/56 ,  G03F9/00 ,  G03F7/00 ,  G03F1/00 ,  G03F1/42

CPC classification number: H01L23/544 ,  G03F1/00 ,  G03F1/42 ,  G03F7/70475 ,  G03F7/70633 ,  G03F9/708 ,  H01L21/56 ,  H01L21/60 ,  H01L2223/54426

Abstract: A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

公开(公告)号：US11676908B2

公开(公告)日：2023-06-13

申请号：US16716167

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chia Hu ,  Chang-Ching Yu ,  Ming-Fa Chen

IPC: H01L23/544 ,  H01L21/56 ,  G03F9/00 ,  G03F7/00 ,  G03F1/00 ,  G03F1/42 ,  H01L21/60

CPC classification number: H01L23/544 ,  G03F1/00 ,  G03F1/42 ,  G03F7/70475 ,  G03F7/70633 ,  G03F9/708 ,  H01L21/56 ,  H01L21/60 ,  H01L2223/54426

Abstract: A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

公开(公告)号：US20190243237A1

公开(公告)日：2019-08-08

申请号：US16315442

申请日：2017-06-26

Applicant: University of Massachusetts

Inventor： James J. Watkins ,  Rohit Kothari

IPC: G03F7/00 ,  B29C71/02 ,  C09D11/52 ,  C09D11/037 ,  C09D11/033

CPC classification number: G03F7/0002 ,  B29C71/02 ,  B29C2071/022 ,  B32B3/10 ,  B32B5/16 ,  B32B5/30 ,  C09D11/033 ,  C09D11/037 ,  C09D11/52 ,  C23C18/06 ,  C23C18/1254 ,  C23C18/1283 ,  G03F1/00 ,  H01L21/02288

Abstract: Various embodiments disclosed relate to methods of manufacturing a textured surface comprising disposing a nanoparticulate ink on a substrate.

公开(公告)号：US20190187567A1

公开(公告)日：2019-06-20

申请号：US16311293

申请日：2017-06-21

Applicant: H.E.F. ,  UNIVERSITE JEAN MONNET SAINT ETIENNE ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)

Inventor： Maxime BICHOTTE ,  Yves JOURLIN ,  Laurent DUBOST

IPC: G03F7/20 ,  G03F9/00 ,  G03F1/76 ,  G03F1/80

CPC classification number: G03F7/70216 ,  B82Y30/00 ,  G03F1/00 ,  G03F1/68 ,  G03F1/76 ,  G03F1/80 ,  G03F7/2026 ,  G03F7/7035 ,  G03F9/70

Abstract: The invention relates to a system (2) for producing an optical mask (35) for surface microtexturing, said system (2) comprising: a substrate (10) having a surface (11) that is to be textured; a layer of material (20) which covers the surface (11) of the substrate (10) and has an outer surface (21) that is exposed to the outside environment; and a generating and depositing device for generating and depositing droplets (30) on the outer surface (21) of the layer of material (20), in a specific arrangement (31) under condensation, forming the optical mask (35) on the outer surface (21) of the layer of material (20). The invention also relates to a treatment plant comprising a system (2) of said type. The invention further relates to a method for producing a mask as well as to a surface microtexturing method.

公开(公告)号：US20180329313A1

公开(公告)日：2018-11-15

申请号：US16042063

申请日：2018-07-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yang-Hung Chang ,  Chih-Ming Ke ,  Kai-Hsiung Chen

IPC: G03F7/20 ,  G06F17/50

CPC classification number: G03F7/70633 ,  G01N37/00 ,  G01P21/00 ,  G01R31/26 ,  G03F1/00 ,  G03F9/00 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/16 ,  G21K5/00 ,  H01L21/00

Abstract: A method for overlay monitoring and control is introduced in the present disclosure. The method includes selecting a group of patterned wafers from a lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming an overlay correction map using the measured overlay errors on the selected wafer; and generating a combined overlay correction map using the overlay correction map of each selected wafer in the lot.

公开(公告)号：US09960193B2

公开(公告)日：2018-05-01

申请号：US15136075

申请日：2016-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Woo Park ,  Siwoo Kim

IPC: H01L21/44 ,  H01L27/12 ,  G03F1/00

CPC classification number: H01L27/124 ,  G03F1/00

Abstract: A display driver integrated circuit and a method of manufacturing the same are provided. The method of manufacturing a display driver integrated circuit (DDI) including a first area, a second area, and an overlapping area in which the first area and the second area overlap each other includes forming a first pattern in the first area using a first reticle; and forming a second pattern in the second area using a second reticle, and ends of the first pattern and the second pattern are connected within the overlapping area and the first area and the second area are asymmetrically set based on the overlapping area such that the overlapping area includes only a metal line.

公开(公告)号：US09806109B2

公开(公告)日：2017-10-31

申请号：US14490814

申请日：2014-09-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Tiansheng Li ,  Zhenyu Xie

IPC: H01L27/14 ,  H01L27/12 ,  H01L21/027 ,  H01L21/3213 ,  G03F1/00

CPC classification number: H01L27/1288 ,  G03F1/00 ,  H01L21/0274 ,  H01L21/32139

Abstract: The present disclosure provides a half tone mask plate used to manufacture an active layer pattern as well as a source electrode pattern, a drain electrode pattern and a data line pattern located on the active layer pattern included in the array substrate. A surface of the array substrate includes a first region corresponding to the source electrode pattern, the drain electrode pattern and the data line pattern, a second region corresponding to a region of the active layer pattern located between the source electrode pattern and the drain electrode pattern, as well as a third region in addition to the first region and the second region; the half tone mask plate includes a semi-transparent region corresponding to the second region and a partial region of the third region.

公开(公告)号：US09767244B2

公开(公告)日：2017-09-19

申请号：US15093646

申请日：2016-04-07

Applicant: Infineon Technologies AG

Inventor： Henning Haffner ,  Manfred Eller ,  Richard Lindsay

IPC: G06F17/50 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/02 ,  G03F1/00 ,  H01L27/082 ,  H01L27/085 ,  H01L21/033 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F2217/12 ,  H01L21/0334 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/082 ,  H01L27/085 ,  H01L27/088 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T29/41

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.