公开(公告)号：US09081634B1

公开(公告)日：2015-07-14

申请号：US13672948

申请日：2012-11-09

Applicant: Xilinx, Inc.

Inventor： James M. Simkins ,  Wayne E. Wennekamp ,  John M. Thendean ,  Adam Elkins ,  Richard L. Walke

IPC: G06F7/57

CPC classification number: G06F7/57 ,  G06F7/4806 ,  G06F7/5443 ,  G06F2207/382 ,  G06F2207/3828

Abstract: An apparatus is disclosed. This apparatus includes a digital signal processing (“DSP”) block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit (“ALU”) block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.

Abstract translation: 公开了一种装置。 该装置包括数字信号处理（“DSP”）块，其具有被耦合以接收第一至第四输入操作数的前置寄存器块。 乘法器耦合到前置寄存器块以接收被乘数的操作数和乘法器操作数。 第一寄存器块耦合到乘法器以从乘法器接收部分乘积的集合。 耦合以接收第三操作数输入的第二寄存器块。 算术逻辑单元（“ALU”）块耦合到预加器寄存器块，第一寄存器块和第二寄存器块。 ALU块包括四个输入多路复用器和一个ALU，其中ALU被耦合以接收四个输入多路复用器中的每一个的输出。