公开(公告)号：US10110234B1

公开(公告)日：2018-10-23

申请号：US15654506

申请日：2017-07-19

Applicant: Xilinx, Inc.

Inventor： Uma E. Durairajan ,  Subodh Kumar ,  Adam Elkins ,  Ghazaleh Mirjafari ,  Amitava Majumdar

IPC: H03K19/177 ,  G01R31/3185

Abstract: Methods and apparatus are described for providing and operating an efficient infrastructure to implement a built-in clock stop and scan dump (CSSD) scheme for fabric blocks, such as block random access memory (BRAM), UltraRAM (URAM), digital signal processing (DSP) blocks, configurable logic elements (CLEs), and the like. This is a very useful feature for system debug and can also be applied for emulation use cases (e.g., FPGA emulation). This scheme can be applied to any tiled architecture that has highly repetitive blocks. The infrastructure may include a DFx controller shared across multiple tiled blocks with some distributed logic in each block, in an effort to minimize or at least reduce area overhead. The infrastructure may also minimize or at least reduce utilization of fabric resources in an effort to ensure the least perturbation of the original design, such that the design issues being debugged can be easily reproduced.

公开(公告)号：US10673438B1

公开(公告)日：2020-06-02

申请号：US16373524

申请日：2019-04-02

Applicant: Xilinx, Inc.

Inventor： Adam Elkins ,  Ephrem C. Wu ,  John M. Thendean ,  Adnan Pratama ,  Yashodhara Parulkar ,  Xiaoqian Zhang

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/17724 ,  G06F7/575 ,  H03K19/1776 ,  G06F7/501 ,  G06F7/523 ,  G06F7/48

Abstract: A digital signal processor (DSP) slice is disclosed. The DSP slice includes an input stage to receive a plurality of input signals, a pre-adder coupled to the input stage and configured to perform one or more operations on one or more of the plurality of input signals, and a multiplier coupled to the input stage and the pre-adder and configured to perform one or more multiplication operations on one or more of the plurality of input signals or the output of the pre-adder. The DSP slice further includes an arithmetic logic unit (ALU) coupled to the input stage, the pre-adder, and the multiplier. The ALU is configured to perform one or more mathematical or logical operations on one or more of the plurality of input signals, the output of the pre-adder, or the output of the multiplier. The DSP slice also includes an output stage coupled to the ALU, the output stage configured to generate one or more output signals based at least in part on one or more of the outputs of the ALU, or at least one of the plurality of input signals.

公开(公告)号：US09081634B1

公开(公告)日：2015-07-14

申请号：US13672948

申请日：2012-11-09

Applicant: Xilinx, Inc.

Inventor： James M. Simkins ,  Wayne E. Wennekamp ,  John M. Thendean ,  Adam Elkins ,  Richard L. Walke

IPC: G06F7/57

CPC classification number: G06F7/57 ,  G06F7/4806 ,  G06F7/5443 ,  G06F2207/382 ,  G06F2207/3828

Abstract: An apparatus is disclosed. This apparatus includes a digital signal processing (“DSP”) block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit (“ALU”) block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.

Abstract translation: 公开了一种装置。 该装置包括数字信号处理（“DSP”）块，其具有被耦合以接收第一至第四输入操作数的前置寄存器块。 乘法器耦合到前置寄存器块以接收被乘数的操作数和乘法器操作数。 第一寄存器块耦合到乘法器以从乘法器接收部分乘积的集合。 耦合以接收第三操作数输入的第二寄存器块。 算术逻辑单元（“ALU”）块耦合到预加器寄存器块，第一寄存器块和第二寄存器块。 ALU块包括四个输入多路复用器和一个ALU，其中ALU被耦合以接收四个输入多路复用器中的每一个的输出。