公开(公告)号：US10943039B1

公开(公告)日：2021-03-09

申请号：US15786105

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Ashish Sirasao ,  Elliott Delaye ,  Sean Settle ,  Zhao Ma ,  Ehsan Ghasemi ,  Xiao Teng ,  Aaron Ng ,  Jindrich Zejda

IPC: G06F30/327 ,  G06F7/544 ,  G06N3/04 ,  G06F30/34

Abstract: An example multiply accumulate (MACC) circuit includes: a multiply-accumulator having an accumulator output register; a quantizer, coupled to the multiply accumulator; and a control circuit coupled to the multiply-accumulator and the quantizer, the control circuit configured to provide control data to the quantizer, the control data indicative of a most-significant bit (MSB) to least significant bit (LSB) range for selecting bit indices from the accumulator output register.

公开(公告)号：US10430539B1

公开(公告)日：2019-10-01

申请号：US15382439

申请日：2016-12-16

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Zhao Ma ,  Krishna Garlapati ,  Ashish Sirasao

IPC: G06F17/50

Abstract: Methods and apparatus relating generally to synthesis are described. In such a method, a directed graph for a circuit design is generated. A cascaded chain is identified in the directed graph with a timing violation. A pipeline register stage of the cascaded chain is moved (or added) to remove the timing violation. The circuit design is transformed to provide a netlist including the pipeline register stage.