公开(公告)号：US20240256749A1

公开(公告)日：2024-08-01

申请号：US18102490

申请日：2023-01-27

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Ruibing Lu ,  Shangzhi Sun ,  Nithin Kumar Guggilla

IPC: G06F30/3312 ,  G06F30/392 ,  G06F30/394

CPC classification number: G06F30/3312 ,  G06F30/392 ,  G06F30/394 ,  G06F2119/12

Abstract: Retiming a circuit design can include determining whether or not an initial value specified for a candidate register can be removed based on an input logic cone to the candidate register and an output logic cone from the candidate register. The candidate register is a register in a critical path in the circuit design. The candidate register can be retimed into a retimed register in response to determining that the initial value specified for the candidate register can be removed. A new initial value for the retimed register can be derived based on initial values of registers in a logic cone of the retimed register, and the new initial value can be assigned to the retimed register.

公开(公告)号：US10366001B1

公开(公告)日：2019-07-30

申请号：US15706255

申请日：2017-09-15

Applicant: Xilinx, Inc.

Inventor： Nithin Kumar Guggilla ,  Chaithanya Dudha ,  Krishna Garlapati ,  Chun Zhang ,  Fan Zhang ,  Anup Kumar Sultania

IPC: G06F12/00 ,  G06F12/02 ,  G06F1/3287 ,  G06F13/00 ,  G06F13/28

Abstract: Disclosed approaches of processing a circuit design include determining a subset of addresses of a first RAM of the circuit design that are accessed more often than a frequency threshold. A specification of a second RAM is created for the subset of addresses. A decoder circuit is added to the circuit design. The decoder circuit is configured to enable the second RAM and disable the first RAM in response to an input address in the subset of addresses, and to enable the first RAM and disable the second RAM in response to an input address other than addresses in the subset of addresses.

公开(公告)号：US10726175B1

公开(公告)日：2020-07-28

申请号：US16291952

申请日：2019-03-04

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Satyaprakash Pareek ,  Bing Tian ,  Ashish Sirasao

IPC: G06F30/30 ,  H01L27/02 ,  G06F30/327 ,  G06F30/398 ,  G06F30/00

Abstract: A memory optimization method includes identifying, within a circuit design, a memory having an arithmetic operator at an output side and/or an input side of the memory. The memory may include a read-only memory (ROM). In some examples, an input of the arithmetic operator includes a constant value. In some embodiments, the memory optimization method further includes absorbing a function of the arithmetic operator into the memory. By way of example, the absorbing the function includes modifying contents of the memory based on the function of the arithmetic operator to provide an updated memory and removing the arithmetic operator from the circuit design.

公开(公告)号：US10606979B1

公开(公告)日：2020-03-31

申请号：US16001206

申请日：2018-06-06

Applicant: Xilinx, Inc.

Inventor： Shangzhi Sun ,  Bing Tian ,  Chaithanya Dudha

IPC: G06F17/50

Abstract: Verifying a circuit design may include, in response to modification of the circuit design involving at least one of inserting or removing a flip-flop, determining, using computer hardware, latency change values for pins of components of the circuit design, determining, using the computer hardware, total latency for the pins of the components of the circuit design based, at least in part, upon the latency change values, and comparing, using the computer hardware, total latency of the pins of the components of the circuit design. Verifying the circuit design may also include detecting, using the computer hardware, a latency error within the circuit design based upon the comparing and generating, using the computer hardware, a notification of the latency error in the circuit design, wherein the notification specifies a type of the latency error detected.

公开(公告)号：US10387600B2

公开(公告)日：2019-08-20

申请号：US15266827

申请日：2016-09-15

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Krishna Garlapati

IPC: G06F17/50 ,  G06F1/32

Abstract: Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.

公开(公告)号：US20250148179A1

公开(公告)日：2025-05-08

申请号：US18503047

申请日：2023-11-06

Applicant: Xilinx, Inc.

Inventor： Pradip Kar ,  Chaithanya Dudha ,  Nithin Kumar Guggilla

IPC: G06F30/327 ,  G06F30/323

Abstract: A memory includes a read circuit having a first primitive configured to output a first data item based on least significant bits (LSBs) of a read address and a multiplexer coupled to the primitive. The multiplexer outputs a selected bit from the first data item as read data based on most significant bits (MSBs) of the read address. The memory includes a write circuit having a second primitive that outputs a second data item based on LSBs of a write address and a modifier circuit that generates a third data item by modifying a bit of the second data item to correspond to write data. The bit is at a location within the second data item selected based on MSBs of the write address. The modifier circuit writes the third data item to a location in the write primitive based on the LSBs of the write address.

公开(公告)号：US11100267B1

公开(公告)日：2021-08-24

申请号：US16867165

申请日：2020-05-05

Applicant: XILINX, INC.

Inventor： Nithin Kumar Guggilla ,  Pradip Kar ,  Chaithanya Dudha

IPC: G06F30/337

Abstract: Embodiments herein describe techniques for designing a compressed hardware implementation of a user-designed memory. In one example, a user defines a memory in hardware description language (HDL) with a depth (D) and a width (W). To compress the memory, a synthesizer designs a core memory array representing the user-defined memory. Using addresses, the synthesizer can identify groups of nodes in the array that can be compressed into a memory element. The synthesizer designs input circuitry such as a data replicator and a write enable generator for generating the inputs and control signals for the groups. The synthesizer can then implement the design in an integrated circuit where each group of nodes maps to a single memory element, thereby resulting in a compressed design.

公开(公告)号：US10430539B1

公开(公告)日：2019-10-01

申请号：US15382439

申请日：2016-12-16

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Zhao Ma ,  Krishna Garlapati ,  Ashish Sirasao

IPC: G06F17/50

Abstract: Methods and apparatus relating generally to synthesis are described. In such a method, a directed graph for a circuit design is generated. A cascaded chain is identified in the directed graph with a timing violation. A pipeline register stage of the cascaded chain is moved (or added) to remove the timing violation. The circuit design is transformed to provide a netlist including the pipeline register stage.

公开(公告)号：US20250005249A1

公开(公告)日：2025-01-02

申请号：US18344766

申请日：2023-06-29

Applicant: Xilinx, Inc.

Inventor： Fan Zhang ,  Chaithanya Dudha ,  Nithin Kumar Guggilla

IPC: G06F30/392

Abstract: Reducing power consumption of a circuit design includes, for a circuit block of a circuit design, where the circuit block has a plurality of signals, selecting one or more signals of the plurality of signals. Prediction and gating circuitry are generated. The prediction and gating circuitry include a predictor circuit configured to generate a prediction of an output of the circuit block based on the one or more signals as selected and gate the circuit block based on the prediction of the output of the circuit block. The prediction and gating circuitry include an output circuit configured to substitute a constant value as the output of the circuit block responsive to gating the circuit block by the predictor circuit. The prediction and gating circuitry are inserted within the circuit design.

公开(公告)号：US20230297824A1

公开(公告)日：2023-09-21

申请号：US17655489

申请日：2022-03-18

Applicant: Xilinx, Inc.

Inventor： Rajeev Patwari ,  Chaithanya Dudha ,  Jorn Tuyls ,  Kaushik Barman ,  Aaron Ng

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: A programmable, non-linear (PNL) activation engine for a neural network is capable of receiving input data within a circuit. In response to receiving an instruction corresponding to the input data, the PNL activation engine is capable of selecting a first non-linear activation function from a plurality of non-linear activation functions by decoding the instruction. The PNL activation engine is capable of fetching a first set of coefficients corresponding to the first non-linear activation function from a memory. The PNL activation engine is capable of performing a polynomial approximation of the first non-linear activation function on the input data using the first set of coefficients. The PNL activation engine is capable of outputting a result from the polynomial approximation of the first non-linear activation function.