公开(公告)号：US08748926B2

公开(公告)日：2014-06-10

申请号：US13720649

申请日：2012-12-19

Applicant: Xintec Inc.

Inventor： Kuo-Hua Liu ,  Yi-Ming Chang ,  Hsi-Chien Lin

IPC: H01L33/00 ,  H01L21/00

CPC classification number: H01L21/78 ,  H01L21/50 ,  H01L21/561 ,  H01L23/10 ,  H01L23/48 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.

Abstract translation: 芯片封装包括：具有第一和第二表面的衬底; 形成在基板上或设置在基板上的器件区域; 设置在所述第一表面上的电介质层; 至少一个导电焊盘，其布置在所述电介质层中并电连接到所述器件区域; 设置在所述电介质层上的平面层，其中所述平面层的上表面与所述导电焊盘之间的垂直距离大于约2μm; 设置在所述第一表面上的透明基板; 设置在所述透明基板和所述平面层之间的第一间隔层; 以及第二间隔层，其设置在所述透明基板和所述基板之间并且延伸到所述电介质层的与所述导电焊盘接触的开口中，其中所述第二间隔层和所述导电焊盘之间基本上没有间隙。

公开(公告)号：US08993365B2

公开(公告)日：2015-03-31

申请号：US14191348

申请日：2014-02-26

Applicant: Xintec Inc.

Inventor： Yi-Ming Chang ,  Kuo-Hua Liu ,  Yi-Cheng Wang ,  Sheng-Yen Chang

IPC: H01L21/00 ,  H01L31/0203 ,  H01L21/683

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/48091 ,  H01L2924/16235 ,  H01L2924/00014

Abstract: A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided. A first surface of the wafer opposite to the integrated circuit units is ground. A release layer is formed on a second surface of a light transmissive carrier. An ultraviolet temporary bonding layer is formed on the second surface of the light transmissive carrier or a third surface of the wafer. The ultraviolet temporary bonding layer is used to adhere the second surface of the light transmissive carrier to the third surface of the wafer. The first surface of the wafer is adhered to an ultraviolet tape. A fourth surface of the light transmissive carrier is exposed to ultraviolet to eliminate adhesion force of the ultraviolet temporary bonding layer. The light transmissive carrier and the release layer are removed.

Abstract translation: 晶片封装方法包括以下步骤。 提供具有多个集成电路单元的晶片。 与集成电路单元相对的晶片的第一表面被研磨。 剥离层形成在透光载体的第二表面上。 在透光载体的第二表面或晶片的第三表面上形成紫外线临时粘接层。 紫外线暂时接合层用于将透光载体的第二表面粘附到晶片的第三表面。 晶片的第一表面粘附到紫外线带上。 透光载体的第四表面暴露于紫外线以消除紫外线临时粘合层的粘附力。 去除透光载体和释放层。