公开(公告)号：US12057538B2

公开(公告)日：2024-08-06

申请号：US17042101

申请日：2019-11-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jianguo Wang ,  Zhanfeng Cao

IPC: H01L33/62 ,  G02F1/1335 ,  G02F1/13357 ,  H01L23/48 ,  H01L25/075

CPC classification number: H01L33/62 ,  G02F1/133603 ,  G02F1/133612 ,  H01L23/48 ,  H01L25/0753

Abstract: A driving substrate, including: a base; a first insulating layer and first conductive wires on the base; the first insulating layer is provided with openings, the first conductive wires are positioned in the openings, and at any position in a lengthwise direction of the first conductive wires, each side surface of each first conductive wire is in contact with a side surface of the opening, where said each first conductive wire is positioned, at least at a partial height; each first conductive wire includes a seed wire and a growth wire; second conductive wires positioned on a side of the first conductive wires away from the base, each second conductive wire is coupled to one first conductive wire and is provided with a coupling area for coupling a light-emitting unit. A method for manufacturing the driving substrate, a light-emitting substrate and a display device are further provided.

公开(公告)号：US12057383B2

公开(公告)日：2024-08-06

申请号：US18148001

申请日：2022-12-29

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Rajesh Katkar ,  Gabriel Z. Guevara ,  Javier A. DeLaCruz ,  Shaowu Huang ,  Laura Willis Mirkarimi

IPC: H01L23/498 ,  H01G2/02 ,  H01G4/12 ,  H01G4/228 ,  H01G4/30 ,  H01G4/38 ,  H01G4/40 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/66 ,  H05K1/18 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01G2/02 ,  H01G4/1245 ,  H01G4/228 ,  H01G4/30 ,  H01G4/40 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L24/08 ,  H01L24/32 ,  H05K1/18 ,  H01G4/38 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/05 ,  H01L24/80 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2224/03845 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/0807 ,  H01L2224/08265 ,  H01L2224/16265 ,  H01L2224/32265 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19103 ,  H05K1/0231 ,  H05K1/185 ,  H05K2201/10015 ,  H01L2224/80203 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05686 ,  H01L2924/05442 ,  H01L2224/80948 ,  H01L2924/00014 ,  H01L2224/05556 ,  H01L2924/00012

Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

公开(公告)号：US20240258234A1

公开(公告)日：2024-08-01

申请号：US18633866

申请日：2024-04-12

Applicant: KIOXIA CORPORATION

Inventor： Kosuke YANAGIDAIRA ,  Chikaaki KODAMA

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L27/02 ,  H10B41/10 ,  H10B41/40 ,  H10B41/41

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/522 ,  H01L27/0207 ,  H10B41/10 ,  H10B41/40 ,  H10B41/41 ,  H01L2924/0002

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

公开(公告)号：US12009332B2

公开(公告)日：2024-06-11

申请号：US16088455

申请日：2016-07-28

Applicant: Mitsubishi Electric Corporation

Inventor： Yosuke Nakata ,  Taishi Sasaki

IPC: H01L23/00 ,  H01L21/52 ,  H01L23/48

CPC classification number: H01L24/32 ,  H01L21/52 ,  H01L23/48 ,  H01L24/29 ,  H01L24/30 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/26155 ,  H01L2224/29155 ,  H01L2224/30181 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83007 ,  H01L2224/83065 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/10272 ,  H01L2924/351

Abstract: A semiconductor chip (3) is bonded to an upper surface of an electrode substrate (1) via a first solder (2). A lead frame (5) is bonded to an upper surface of the semiconductor chip (3) via a second solder (4). An intermediate plate (6) is provided in the first solder (2) between the electrode substrate (1) and the semiconductor chip (3). A yield strength of the intermediate plate (6) is higher than yield strengths of the electrode substrate (1) and the first solder (2) within the whole operating temperature range of the semiconductor device.

公开(公告)号：US11990406B2

公开(公告)日：2024-05-21

申请号：US17860345

申请日：2022-07-08

Applicant: KIOXIA CORPORATION

Inventor： Kosuke Yanagidaira ,  Chikaaki Kodama

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L27/02 ,  H10B41/10 ,  H10B41/40 ,  H10B41/41

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/522 ,  H01L27/0207 ,  H10B41/10 ,  H10B41/40 ,  H10B41/41 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

公开(公告)号：USRE49773E1

公开(公告)日：2024-01-02

申请号：US17323779

申请日：2021-05-18

Applicant: NANOPAREIL, LLC

Inventor： Todd J. Menkhaus ,  Hao Fong

IPC: B01D39/16 ,  B01D15/32 ,  B01D15/36 ,  B01D15/38 ,  B01J20/24 ,  B01J20/28 ,  B01J20/32 ,  C07K1/22 ,  D01D5/00 ,  D01F2/24 ,  D01F6/44 ,  D01F6/88 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: B01D39/1615 ,  B01D15/327 ,  B01D15/361 ,  B01D15/3809 ,  B01D39/1623 ,  B01D39/1676 ,  B01J20/24 ,  B01J20/28007 ,  B01J20/28038 ,  B01J20/3212 ,  B01J20/3217 ,  B01J20/3248 ,  B01J20/3293 ,  C07K1/22 ,  D01D5/003 ,  D01D5/0007 ,  D01F2/24 ,  D01F6/44 ,  D01F6/88 ,  H01L23/48 ,  H01L24/72 ,  H01L24/73 ,  H01L24/90 ,  H01L24/91 ,  H01L25/0652 ,  H01L25/50 ,  B01D15/3804 ,  B01D2239/025 ,  B01D2239/0414 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/73201 ,  H01L2224/81138 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/157 ,  H01L2924/1579 ,  H01L2924/15153 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/73201 ,  H01L2224/16 ,  H01L2224/72 ,  H01L2224/9211 ,  H01L2224/81 ,  H01L2224/90 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81138 ,  H01L2924/00012

Abstract: The present invention relates generally to compositions for use in biological and chemical separations, as well as other applications. More specifically, the present invention relates to hybrid felts fabricated from electrospun nanofibers with high permeance and high capacity. Such hybrid felts utilize derivatized cellulose, and at least one non-cellulose-based polymer that may be removed from the felt by subjecting it to moderately elevated temperatures and/or solvents capable of dissolving the non-cellulose-based polymer to leave behind a porous nanofiber felt having more uniform pore sizes and other enhanced properties when compared to single component nanofiber felts.

公开(公告)号：US11855033B2

公开(公告)日：2023-12-26

申请号：US17440790

申请日：2019-05-30

Applicant: Mitsubishi Electric Corporation

Inventor： Haruko Hitomi ,  Kozo Harada ,  Ken Sakamoto

IPC: H01L23/00 ,  H01L23/18 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L24/48 ,  H01L23/18 ,  H01L23/3107 ,  H01L23/48 ,  H01L24/85 ,  H01L2224/48227 ,  H01L2224/85909 ,  H01L2924/181

Abstract: The conductive wire is bonded to the front electrode of the semiconductor device at the bonding section. The first resin member covers at least one end portion of two end portions of the bonding section, the first surface of the front electrode, and the second surface of the conductive wire. The second resin member covers the bent portion of the first resin member. The first resin member has a higher break elongation and a higher break strength than the second resin member. The second tensile elastic modulus of the second resin member is greater than the first tensile elastic modulus of the first resin member. Thereby, the reliability of the power semiconductor module is improved.

公开(公告)号：US20230317591A1

公开(公告)日：2023-10-05

申请号：US18148001

申请日：2022-12-29

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba ,  llyas Mohammed ,  Rajesh Katkar ,  Gabriel Z. Guevara ,  Javier A. DeLaCruz ,  Shaowu Huang ,  Laura Willis Mirkarimi

IPC: H01L23/498 ,  H01L23/00 ,  H01G4/30 ,  H01G4/228 ,  H01G4/12 ,  H01G4/40 ,  H05K1/18 ,  H01L23/48 ,  H01G2/02 ,  H01L23/522

CPC classification number: H01L23/49838 ,  H01L24/08 ,  H01L24/32 ,  H01L23/49827 ,  H01G4/30 ,  H01G4/228 ,  H01G4/1245 ,  H01G4/40 ,  H05K1/18 ,  H01L23/48 ,  H01G2/02 ,  H01L23/5223 ,  H01L23/49822 ,  H05K2201/10015 ,  H01L24/05 ,  H01L23/66

Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

公开(公告)号：US20230296839A1

公开(公告)日：2023-09-21

申请号：US18324212

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Chang Chang ,  Meng-Han Lin

IPC: G02B6/124 ,  H01L23/48 ,  G02B6/136

CPC classification number: G02B6/124 ,  H01L23/48 ,  G02B6/136 ,  G02B6/12019

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an optical device disposed on a substrate. A dielectric structure overlies the substrate. The dielectric structure comprises one or more sidewalls defining a light channel over a region of the optical device. A protective structure is above the optical device and disposed on opposing sides of the light channel.

公开(公告)号：US20190252954A1

公开(公告)日：2019-08-15

申请号：US16395481

申请日：2019-04-26

Applicant: DENSO CORPORATION

Inventor： Masayoshi NISHIHATA ,  Nobumasa UEDA ,  Hiroki KIYOSE

IPC: H02K11/33 ,  H02K3/50 ,  H01L23/367 ,  H01L23/50 ,  H01L25/07

CPC classification number: H02K11/33 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/48 ,  H01L23/50 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/40245 ,  H02K3/50 ,  H02K2203/09 ,  H02M7/48

Abstract: A semiconductor device includes: a plurality of control modules that controls a rotating electric machine. Each control module includes at least two sets of arms, each set including high-side and low-side switching elements that provide an inverter. A plurality of arms of each control module are coupled in parallel to each other with respect to a bus bar coupled to one power source. Each control module includes a metal plate on which the high-side and low-side switching elements are mounted, and mediates an electric coupling with the power source. Each metal plate includes a first metal plate on which one set of arms is disposed, a second metal plate on which another set of arms is disposed, and a coupling plate that couples the first and second metal plates.