公开(公告)号：US20120112362A1

公开(公告)日：2012-05-10

申请号：US13290379

申请日：2011-11-07

Applicant: Yong Chul SHIN

Inventor： Yong Chul SHIN

IPC: H01L23/522 ,  H01L21/76 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in parallel between the first line pattern and the second line pattern, fourth line patterns formed in parallel between the first line pattern and the second line pattern, a first connection structure configured to couple a first of the third line patterns with a first of the fourth lines patterns, which are adjacent to the first line pattern, and a second connection structure configured to couple a second of the first lines patterns with a second of the fourth lines patterns, which are adjacent to the second line pattern.

Abstract translation: 半导体器件包括在半导体衬底上平行形成的第一线图形和第二线图案，平行形成在第一线图案和第二线图案之间的第三线图案，第一线图案和 所述第二线图案，被配置为将所述第三线图案中的第一线图案与所述第一线图案相邻的所述第四线图案中的第一线图案耦合的第一连接结构;以及第二连接结构， 具有与第二线图案相邻的第四线图案中的第二线图案的线图案。

公开(公告)号：US20090186477A1

公开(公告)日：2009-07-23

申请号：US12345612

申请日：2008-12-29

Applicant: Yong Chul SHIN ,  Tae Kyung KIM

Inventor： Yong Chul SHIN ,  Tae Kyung KIM

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76802 ,  H01L23/485 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming metal wirings of a nonvolatile memory device include forming a first insulating layer over a semiconductor substrate including a first junction area and a second junction area, forming first and second contact holes through which the first and second junction areas are respectively exposed in the first insulating layer, forming first and second contact plugs within the first and second contact holes, etching a part of the second contact plug, thus forming a recess, forming a second insulating layer to fill the recess, forming a third insulating layer over the semiconductor substrate including the first and second insulating layers, forming a first trench through which the first contact plug is exposed a second trench through which the second contact plug is exposed by etching the third insulating layer, and forming first and second metal wirings within the first and second trenches, respectively.

Abstract translation: 形成非易失性存储器件的金属配线的方法包括在包括第一接合区域和第二接合区域的半导体衬底上形成第一绝缘层，形成第一和第二接触孔，第一和第二接合区域分别通过该接触孔暴露在 第一绝缘层，在第一和第二接触孔内形成第一和第二接触塞，蚀刻第二接触塞的一部分，从而形成凹陷，形成第二绝缘层以填充凹部，在第 包括所述第一和第二绝缘层的半导体衬底，形成第一沟槽，所述第一接触插塞通过所述第一沟槽露出第二沟槽，所述第二接触插塞通过蚀刻所述第三绝缘层而暴露在所述第二沟槽中;以及在所述第一沟槽内形成第一和第二金属布线 和第二个沟槽。