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6 条记录 (耗时 0.028 秒)

    Global bit line restore timing scheme and circuit
    2.
    发明授权
    Global bit line restore timing scheme and circuit 失效
    全局位线恢复时序方案和电路

    公开(公告)号：US07272030B2

    公开(公告)日：2007-09-18

    申请号：US11554072

    申请日：2006-10-30

    申请人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella ,  Uma Srinivasan ,  Arthur D. Tuminaro ,  Jatinder K. Wadhwa

    发明人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella ,  Uma Srinivasan ,  Arthur D. Tuminaro ,  Jatinder K. Wadhwa

    IPC分类号： G11C11/00

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/417

    摘要： A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck1), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

    摘要翻译： 多米诺SRAM阵列恢复脉冲发生系统通过与恢复脉冲相同的本地时钟启动工作解码线，从而消除了字线选择的任何种族问题。 该系统允许全局位选择（或列选择）通过释放复位信号（具有最早到达的阵列时钟ck 1）来快速激活，同时保证使用位解码系统几乎完美的跟踪。 这允许最广泛的写入窗口; 全局列中最早发布预充电选择，仅在位解码系统被禁用后进行复位。

    Split L2 latch with glitch free programmable delay
    3.
    发明授权
    Split L2 latch with glitch free programmable delay 失效
    分离L2锁存器，无毛刺可编程延迟

    公开(公告)号：US07293209B2

    公开(公告)日：2007-11-06

    申请号：US11054311

    申请日：2005-02-09

    申请人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella

    发明人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318552

    摘要： A programmable delay circuit that delays the C2 clock signal by a variable amount that allows the output from the L1 latch to be captured even when there is a large delta between the L1 latch and its L2 latch. This allows the C2 signal to be adjusted within the system dependent upon the amount of cycle steal is needed. The C2 clock delay is inhibited during scan operation to prevent glitches and the trailing edge of the delayed C2 is controlled to maintain a constant C2 duty cycle.

    摘要翻译： 一种可编程延迟电路，其将C 2时钟信号延迟可变量，即使在L 1锁存器和其L 2锁存器之间存在大的增量时，允许来自L 1锁存器的输出被捕获。 这允许在系统内调整C 2信号，这取决于所需的循环窃取量。 在扫描操作期间，C 2时钟延迟被禁止以防止毛刺，并且延迟的C 2的后沿被控制以保持恒定的C 2占空比。

    Global bit line restore timing scheme and circuit
    4.
    发明授权
    Global bit line restore timing scheme and circuit 失效
    全局位线恢复时序方案和电路

    公开(公告)号：US07170774B2

    公开(公告)日：2007-01-30

    申请号：US11054479

    申请日：2005-02-09

    申请人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella ,  Uma Srinivasan ,  Arthur D. Tuminaro ,  Jatinder K. Wadhwa

    发明人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella ,  Uma Srinivasan ,  Arthur D. Tuminaro ,  Jatinder K. Wadhwa

    IPC分类号： G11C11/00

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/417

    摘要： A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

    摘要翻译： 多米诺SRAM阵列恢复脉冲发生系统通过与恢复脉冲相同的本地时钟启动字解码线，从而消除了字线选择的任何种族问题。 该系统允许全局位选择（或列选择）通过释放复位信号（具有最早到达的阵列时钟ckl）来快速激活，同时保证与位解码系统几乎完美的跟踪。 这允许最广泛的写入窗口; 全局列中最早发布预充电选择，仅在位解码系统被禁用后进行复位。

    Local bit select with suppression of fast read before write
    6.
    发明授权
    Local bit select with suppression of fast read before write 失效
    本地位选择与写入前禁止快速读取

    公开(公告)号：US07113433B2

    公开(公告)日：2006-09-26

    申请号：US11054402

    申请日：2005-02-09

    申请人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella ,  Arthur D. Tuminaro

    发明人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella ,  Arthur D. Tuminaro

    IPC分类号： G11C7/00

    CPC分类号： G11C11/413 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

    摘要： A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors. Separate read and write global “bit line” pairs allow the read and write performance to be optimized independently.

    摘要翻译： 多米诺SRAM提供有有源上拉PFET器件，它们淹没“读写速度慢但读取速度非常快”，并允许单元从定时不匹配情况中恢复。 这种方法允许传统的“位选择”钳位通过“有线或”PFET上拉晶体管主动地控制“局部选择”。 单独的读写全局“位线”对可以独立优化读写性能。