公开(公告)号：US20190372578A1

公开(公告)日：2019-12-05

申请号：US16478385

申请日：2018-01-23

Applicant: AMS AG

Inventor： Jia Sheng CHEN ,  Gregor SCHATZBERGER

IPC: H03L7/099 ,  H03L7/093 ,  H03L1/00

Abstract: The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320). The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a current-controlled oscillator (318). For calibration the VCO is electrically disconnected from the loop filter and from the feedback loop, a constant reference voltage is applied to the voltage input (IN), a center frequency programming code (L) is applied to the trimming circuit, the center frequency programming code is iteratively adjusted until a desired center frequency is obtained, a gain programming code (K) is applied to the trimming circuit while the adjusted code is still applied, and the gain programming code is iteratively adjusted until a desired gain is obtained. Then the VCO is connected to the PLL, which is then ready for normal operation.

公开(公告)号：US20150171791A1

公开(公告)日：2015-06-18

申请号：US14572727

申请日：2014-12-16

Applicant: ams AG

Inventor： Gregor SCHATZBERGER

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03K3/26 ,  H03K4/501

Abstract: An oscillator circuit (10) comprises a current path (100) including a capacitor (110) having a first side (S110a) and a second side (S110b), wherein each of the first and second side (S110a, S110b) of the capacitor (110) is selectively connectable to at least a first supply terminal (VD) to apply a first voltage potential (VDDA) or a second supply terminal (VS) to apply a second voltage potential (VSS). The oscillator circuit (10) comprises a comparator (200) having a first input terminal (I200a) being selectively connectable to the first or the second side (S110a, S110b) of the capacitor (110), and a second input terminal (I200b) being connected to a terminal (VR) to apply a reference voltage (VREF). An output signal (OUT, OUTB) of the oscillator circuit is generated in dependence on a comparator output signal (VCFF) of the comparator (200).

Abstract translation: 振荡器电路（10）包括电流路径（100），其包括具有第一侧（S110a）和第二侧（S110b）的电容器（110），其中电容器的第一侧和第二侧（S110a，S110b） （110）可选择性地连接到至少第一电源端子（VD）以施加第一电压电位（VDDA）或第二电源端子（VS）以施加第二电压电位（VSS）。 振荡器电路（10）包括比较器（200），其具有可选择地连接到电容器（110）的第一或第二侧（S110a，S110b）的第一输入端子（I200a）和第二输入端子（I200b） 连接到端子（VR）以施加参考电压（VREF）。 根据比较器（200）的比较器输出信号（VCFF），产生振荡电路的输出信号（OUT，OUTB）。

公开(公告)号：US20200051650A1

公开(公告)日：2020-02-13

申请号：US16488745

申请日：2018-02-27

Applicant: ams AG

Inventor： Gregor SCHATZBERGER ,  Friedrich Peter LEISENBERGER ,  Peter SARSON

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/04 ,  G11C29/38

Abstract: A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.

公开(公告)号：US20130300495A1

公开(公告)日：2013-11-14

申请号：US13892176

申请日：2013-05-10

Applicant: ams AG

Inventor： Gregor SCHATZBERGER

IPC: H02M3/07

CPC classification number: H02M3/07 ,  H02M2001/0045 ,  H02M2001/007

Abstract: A charge pump circuit (11) comprises a first stage (31) and at least a second stage (32), each having a capacitor (130, 230) and a current source (100, 200). The charge pump circuit (11) is configured such that, in a first phase (A) of operation, the capacitor (130) of the first stage (31) is switched in series to the current source (100) of the first stage (31) and the capacitor (230) of the second stage (32) is switched in series to the current source (200) of the second stage (32) and that, in a second phase (B) of operation, the capacitor (130) of the first stage (31) and the capacitor (230) of the second stage (32) are switched in series for providing a supply voltage (VHF) at an output (15) of the charge pump circuit (11). A comparator signal (SCOM) is generated by comparing a voltage at an electrode of one of the capacitors (130, 230) of the first and the at least second stage (31, 32) with a reference voltage (VR). The first and the second phase (A, B) are set depending on the comparator signal (SCOM).

Abstract translation: 电荷泵电路（11）包括第一级（31）和至少第二级（32），每级具有电容器（130,230）和电流源（100,200）。 电荷泵电路（11）被配置为使得在第一阶段（A）中，第一级（31）的电容器（130）与第一级的电流源（100）串联切换 31）和第二级（32）的电容器（230）与第二级（32）的电流源（200）串联切换，并且在第二阶段（B）中，电容器（130） ）和第二级（32）的电容器（230）串联切换，以在电荷泵电路（11）的输出端（15）提供电源电压（VHF）。 通过将第一和至少第二级（31,32）的电容器（130,230）中的一个的电极的电压与参考电压（VR）进行比较来产生比较器信号（SCOM）。 第一和第二相（A，B）根据比较器信号（SCOM）设置。