公开(公告)号：US20200051650A1

公开(公告)日：2020-02-13

申请号：US16488745

申请日：2018-02-27

Applicant: ams AG

Inventor： Gregor SCHATZBERGER ,  Friedrich Peter LEISENBERGER ,  Peter SARSON

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/04 ,  G11C29/38

Abstract: A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.