公开(公告)号：US4644489A

公开(公告)日：1987-02-17

申请号：US579091

申请日：1984-02-10

Applicant: Richard R. Curtin ,  Paul M. Clemente

Inventor： Richard R. Curtin ,  Paul M. Clemente

IPC: G06F7/38 ,  G06F5/00 ,  G06F7/00 ,  G06F7/48 ,  G06F7/491 ,  G06F7/493 ,  G06F7/575

CPC classification number: G06F7/491 ,  G06F7/575

Abstract: Digital circuitry performs arithmetic operations upon first and second binary coded decimal digit strings input thereto. The digital circuitry provides for receiving and storing a first and second BCD digit, the digits having an arbitrary data type format. The first and second data types are selected from the group of packed and unpacked data. The circuitry then performs the arithmetic operation upon the stored BCD digits to obtain a result data word which is made available in a data type format corresponding to a selected one of the input BCD digits. In a particular embodiment, a plurality of the circuits can be operated in a digit slice structure. The digit slice structure operates upon strings of packed, unpacked, and mixed data type arithmetic operands and provides, at its output lines, output data in a format corresponding to a selected input data type. In particular, a unique interconnection of the plural output lines of the circuitry enables the output data type to be packed or unpacked as desired. The circuitry also provides for automatic selection of digits applied to the circuitry thereby relieving the operating environment from significant time consuming and costly supervision.

Abstract translation: 数字电路对输入到其的第一和第二二进制编码十进制数字串进行算术运算。 数字电路提供接收和存储第一和第二BCD数字，这些数字具有任意的数据类型格式。 第一和第二数据类型是从打包和解压缩数据组中选择的。 然后，电路对所存储的BCD数字执行算术运算，以获得结果数据字，该结果数据字以对应于输入BCD数字中所选择的一个的数据类型格式可用。 在特定实施例中，多个电路可以以数字切片结构操作。 数字切片结构对打包的，未打包的和混合的数据类型的算术运算符的串进行操作，并且在其输出行提供与所选择的输入数据类型对应的格式的输出数据。 特别地，电路的多个输出线的独特互连使得输出数据类型能够根据需要被打包或解包。 电路还提供自动选择应用于电路的数字，从而减轻操作环境的耗时和昂贵的监督。

公开(公告)号：US4587610A

公开(公告)日：1986-05-06

申请号：US578796

申请日：1984-02-10

Applicant: Paul K. Rodman

Inventor： Paul K. Rodman

IPC: G06F12/10

CPC classification number: G06F12/1054

Abstract: An address translation method and apparatus is disclosed for use in an auxiliary memory of a computer, which stores data in association with a tag defining its location in a main memory, and also includes a buffer for storing a plurality of addresses together with translations of the corresponding main memory locations, permitting data obtained from the auxiliary memory to be validated by comparing the tag with the translation from the buffer. An improvement in the auxiliary memory is disclosed consisting of a content addressable memory (CAM) for storing translations not found in the buffer. The CAM is adapted so that it can be searched for a translation and the translation, if found in the CAM, is employed to verify data in the auxiliary memory.

Abstract translation: 公开了一种用于计算机的辅助存储器中的地址转换方法和装置，其存储与在主存储器中定义其位置的标签相关联的数据，并且还包括用于存储多个地址以及 相应的主存储器位置，允许通过将标签与来自缓冲器的翻译进行比较来验证从辅助存储器获得的数据。 公开了一种用于存储缓冲器中未找到的翻译的内容可寻址存储器（CAM）的辅助存储器的改进。 CAM适于使其可以被搜索以进行翻译，并且如果在CAM中发现，则使用翻译来验证辅助存储器中的数据。

公开(公告)号：US4561619A

公开(公告)日：1985-12-31

申请号：US578795

申请日：1984-02-10

Applicant: David R. Robillard ,  Robert J. Bullock ,  Jerry C. Marino

Inventor： David R. Robillard ,  Robert J. Bullock ,  Jerry C. Marino

IPC: A47B21/03 ,  F16M11/04 ,  E04G3/00

CPC classification number: F16M11/42 ,  A47B21/03 ,  F16M11/048 ,  A47B2200/0038 ,  Y10S248/918 ,  Y10S248/92 ,  Y10S248/921

Abstract: A support for a CRT monitor provides translational movement for the monitor in two perpendicular directions. The support is on rollers for movement over a horizontal surface, and includes telescoping arms for movement in a first direction. One of the arms enters an elongate guide channel mountable on the surface and includes rollers for rolling along a vertical wall of the channel so that the support moves in a second direction perpendicular to the first. The channel includes a cover and end walls.

Abstract translation: CRT显示器的支持为两个垂直方向的显示器提供平移运动。 所述支撑件是用于在水平表面上运动的滚子，并且包括用于沿第一方向移动的伸缩臂。 一个臂进入可安装在表面上的细长引导通道，并且包括用于沿着通道的垂直壁滚动的辊，使得支撑件沿垂直于第一方向的第二方向移动。 通道包括盖和端壁。

公开(公告)号：US4561051A

公开(公告)日：1985-12-24

申请号：US578797

申请日：1984-02-10

Applicant: Paul K. Rodman ,  Joseph L. Ardini, Jr. ,  David B. Papworth

Inventor： Paul K. Rodman ,  Joseph L. Ardini, Jr. ,  David B. Papworth

IPC: G06F15/16 ,  G06F12/00 ,  G06F12/08 ,  G06F15/177 ,  G06F13/00

CPC classification number: G06F12/084

Abstract: A multiprocessor data processing system in which a number of independent processors can concurrently operate on a shared memory even when one processor is performing a read-modify-write (RMW) operation, the system having a locking, content-associative write buffer and a controller for identifying RMW requests, for addressing the buffer and, for issuing directives to lock the buffer, to validate particular data blocks in the buffer and to transfer data back and forth between the processors, the memory and the buffer.

Abstract translation: 一种多处理器数据处理系统，其中即使当一个处理器执行读 - 修改 - 写（RMW）操作时，多个独立处理器也可以并发地在共享存储器上操作，所述系统具有锁定，内容相关写入缓冲器和控制器 用于识别RMW请求，用于寻址缓冲器，以及用于发出锁定缓冲器的指令，以验证缓冲器中的特定数据块并在处理器，存储器和缓冲器之间来回传送数据。

公开(公告)号：US4536876A

公开(公告)日：1985-08-20

申请号：US579088

申请日：1984-02-10

Applicant: Richard G. Bahr ,  Thomas C. Hogan

Inventor： Richard G. Bahr ,  Thomas C. Hogan

IPC: H04J3/06 ,  H04L7/033 ,  H04L7/04 ,  H04L12/42 ,  H04J3/00

CPC classification number: H04L12/422 ,  H04J3/0685 ,  H04L7/0337 ,  H04L7/046

Abstract: A communications network including a plurality of terminals coupled together to provide a unidirectional communications ring. Each of the terminals is coupled in series along the ring. Each terminal is adapted to transmit (at an associated data rate) a digital signal to the next downstream terminal on the ring. Each terminal is adapted to receive a digital signal at the data rate associated with the next upstream terminal. The received digital signal is applied to a phase locked loop characterized by a hold time which exceeds its lock time. The phase locked loop extracts a local timing signal for re-clocking the received digital signal. The transmission time of N bits is less than the hold time of the phase locked loop. Each terminal monitors the re-clocked signal to identify when same valued consecutive bits are received for a period less than the phase locked loop hold time, and upon such detection to cause that terminal to generate at least one transition.

Abstract translation: 一种通信网络，包括耦合在一起以提供单向通信环的多个终端。 每个端子沿着环串联耦合。 每个终端适于将数字信号（以相关联的数据速率）发送到环上的下一个下游终端。 每个终端适于以与下一个上游终端相关联的数据速率接收数字信号。 接收的数字信号被施加到锁相环，其特征在于超过其锁定时间的保持时间。 锁相环提取本地定时信号，用于对所接收的数字信号进行重新计时。 N位的传输时间小于锁相环的保持时间。 每个终端监视重新计时的信号，以便在小于锁相环保持时间的时间段内接收相同值的连续比特，并且在这种检测时，使该终端产生至少一个转换。