公开(公告)号：US12124530B2

公开(公告)日：2024-10-22

申请号：US17675729

申请日：2022-02-18

申请人： UNTETHER AI CORPORATION

发明人： William Martin Snelgrove

IPC分类号： G06F17/16 ,  G06F7/53 ,  G06F7/544 ,  G06F7/575 ,  G06F9/30

CPC分类号： G06F17/16 ,  G06F7/5324 ,  G06F7/5443 ,  G06F7/575 ,  G06F9/30101

摘要： A processing device includes a two-dimensional array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The device further includes interconnections among the two-dimensional array of processing elements to provide direct communication among neighboring processing elements of the two-dimensional array of processing elements. A processing element of the two-dimensional array of processing elements is connected to a first neighbor processing element that is immediately adjacent the processing element in a first dimension of the two-dimensional array. The processing element is further connected to a second neighbor processing element that is immediately adjacent the processing element in a second dimension of the two-dimensional array.

公开(公告)号：US20240320184A1

公开(公告)日：2024-09-26

申请号：US18620284

申请日：2024-03-28

申请人： Intel Corporation

发明人： Altug Koker ,  Ben Ashbaugh ,  Scott Janus ,  Aravindh Anantaraman ,  Abhishek R. Appu ,  Niranjan Cooray ,  Varghese George ,  Arthur Hunter ,  Brent E. Insko ,  Elmoustapha Ould-Ahmed-Vall ,  Selvakumar Panneer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Kamal Sinha ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Saurabh Tangri

IPC分类号： G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

公开(公告)号：US12099461B2

公开(公告)日：2024-09-24

申请号：US17431034

申请日：2020-03-14

申请人： Intel Corporation

发明人： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Lakshminarayanan Striramassarma ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter ,  Prasoonkumar Surti ,  David Puffer ,  James Valerio ,  Ankur N. Shah

IPC分类号： G06F16/00 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240311626A1

公开(公告)日：2024-09-19

申请号：US18674632

申请日：2024-05-24

申请人： NVIDIA Corporation

发明人： William James Dally ,  Rangharajan Venkatesan ,  Brucek Kurdo Khailany ,  Stephen G. Tell

IPC分类号： G06N3/063 ,  G06F7/544 ,  G06F7/575 ,  G06F17/16 ,  G06N3/02 ,  G06N3/045

CPC分类号： G06N3/063 ,  G06F7/575 ,  G06F17/16 ,  G06N3/02 ,  G06F7/5443 ,  G06N3/045

摘要： Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.

公开(公告)号：US20240311187A1

公开(公告)日：2024-09-19

申请号：US18676283

申请日：2024-05-28

申请人： Imagination Technologies Limited

发明人： Simon Nield ,  Yoong-Chert Foo ,  Adam de Grasse ,  Luca Iuliano

IPC分类号： G06F9/48 ,  G06F7/575 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/4881 ,  G06F7/575 ,  G06F9/3001 ,  G06F9/3016 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3867

摘要： A method of scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state, and checking, by an instruction controller, if an ALU targeted by the decoded instruction is a primary instruction pipeline. If the targeted ALU is a primary instruction pipeline, a list associated with the primary instruction pipeline is checked to determine whether the scheduled task is already included in the list. If the scheduled task is already included in the list, the decoded instruction is sent to the primary instruction pipeline.

公开(公告)号：US20240296330A1

公开(公告)日：2024-09-05

申请号：US18664035

申请日：2024-05-14

申请人： Tesla, Inc.

发明人： Forrest Nelson Iandola ,  Harsimran Singh Sidhu ,  Yiqi Hou

IPC分类号： G06N3/08 ,  G06F7/575

CPC分类号： G06N3/08 ,  G06F7/575

摘要： A neural network architecture is used that reduces the processing load of implementing the neural network. This network architecture may thus be used for reduced-bit processing devices. The architecture may limit the number of bits used for processing and reduce processing to prevent data overflow at individual calculations of the neural network. To implement this architecture, the number of bits used to represent inputs at levels of the network and the related filter masks may also be modified to ensure the number of bits of the output does not overflow the resulting capacity of the reduced-bit processor. To additionally reduce the load for such a network, the network may implement a “starconv” structure that permits the incorporation of nearby nodes in a layer to balance processing requirements and permit the network to learn from context of other nodes.

公开(公告)号：US11934698B2

公开(公告)日：2024-03-19

申请号：US17556503

申请日：2021-12-20

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Sooraj Puthoor ,  Muhammad Amber Hassaan ,  Ashwin Aji ,  Michael L. Chu ,  Nuwan Jayasena

IPC分类号： G06F3/06 ,  G06F7/575

CPC分类号： G06F3/0659 ,  G06F3/0622 ,  G06F3/0631 ,  G06F3/0656 ,  G06F3/0679 ,  G06F7/575

摘要： Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

公开(公告)号：US11934668B2

公开(公告)日：2024-03-19

申请号：US17202591

申请日：2021-03-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyunsoo Kim ,  Seungwon Lee ,  Yuhwan Ro

IPC分类号： G06F3/06 ,  G06F7/575 ,  G06N3/02

CPC分类号： G06F3/0626 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F7/575 ,  G06N3/02

摘要： A method of operating a storage device includes storing received input data of a first format, converting the input data into a second format for an operation to be performed on the input data of the second format using an operator included in the storage device, and converting the input data into a second format for an operation to be performed on the input data, through an operator included in the storage device, and re-storing the input data of the second format.

公开(公告)号：US11899614B2

公开(公告)日：2024-02-13

申请号：US17849201

申请日：2022-06-24

申请人： Intel Corporation

发明人： Joydeep Ray ,  Altug Koker ,  Varghese George ,  Mike Macpherson ,  Aravindh Anantaraman ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Nicolas Galoppo von Borries ,  Ben J. Ashbaugh

IPC分类号： G06F15/78 ,  G06F9/30 ,  G06F9/38 ,  G06F17/18 ,  G06F12/0802 ,  G06F7/544 ,  G06F7/575 ,  G06F12/02 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/128 ,  G06F12/06 ,  G06F12/1009 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F12/0811 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58 ,  G06F12/0871 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/50 ,  G06F12/0804 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0888 ,  G06T15/06 ,  G06N3/08

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

公开(公告)号：US11886491B2

公开(公告)日：2024-01-30

申请号：US17326565

申请日：2021-05-21

申请人： SAMSUNG ELECTRONICS CO., LTD. ,  University of Seoul Industry Cooperation Foundation

发明人： Myungjae Jeon ,  Kichul Kim ,  Yongkyu Kim ,  Hongseok Lee ,  San Kim ,  Hyekwan Yun ,  Donggeun Lee

IPC分类号： G06F16/56 ,  G06F5/01 ,  G06F7/50 ,  G06F7/78 ,  G06F17/16 ,  G06F7/575

CPC分类号： G06F16/56 ,  G06F5/01 ,  G06F7/50 ,  G06F7/575 ,  G06F7/78 ,  G06F17/16

摘要： A preconditioned conjugate gradient (PCG) solver, embedded in an electronic device to perform a simultaneous localization and mapping (SLAM) operation, includes an image database, a factor graph database, and a back-end processor, wherein the back-end processor is configured to receive an image from the image database to perform re-localization, receive, from the factor graph database, data for calculating six degrees of freedom (DoF)-related components, construct a matrix including the six degrees of freedom-related components based on the received data, and load and rearrange the matrix and a vector, to perform calculation on each block of each row of the matrix and the vector, then output first data, and shift second data to a location of the first data.