Deposition method for nanostructure materials
    91.
    发明申请
    Deposition method for nanostructure materials 有权
    纳米结构材料的沉积方法

    公开(公告)号:US20080006534A1

    公开(公告)日:2008-01-10

    申请号:US11266318

    申请日:2005-11-04

    IPC分类号: C25B7/00

    CPC分类号: C25D13/00 B82Y30/00 C25D15/00

    摘要: A method for depositing a coating of a nanostructure material onto a substrate includes: (1) forming a solution or suspension of containing the nanostructure material; (2) selectively adding “chargers” to the solution; (3) immersing electrodes in the solution, the substrate upon which the nanostructure material is to be deposited acting as one of the electrodes; (4) applying a direct and/or alternating current electrical field between the two electrodes for a certain period of time thereby causing the nanostructure materials in the solution to migrate toward and attach themselves to the substrate electrode; and (5) subsequent optional processing of the coated substrate.

    摘要翻译: 将纳米结构材料的涂层沉积在基材上的方法包括:(1)形成含有纳米结构材料的溶液或悬浮液; (2)选择性地将“充电器”添加到解决方案中; (3)将电极浸渍在溶液中,沉积纳米结构材料的基板作为其中一个电极; (4)在两个电极之间施加直接和/或交流的电场一段时间,从而导致溶液中的纳米结构材料迁移并附着到衬底电极上; 和(5)随后可选地处理涂覆的基底。

    CMOS circuit of GaAs/Ge on Si substrate
    92.
    发明授权
    CMOS circuit of GaAs/Ge on Si substrate 有权
    GaAs / Ge在Si衬底上的CMOS电路

    公开(公告)号:US06689677B2

    公开(公告)日:2004-02-10

    申请号:US10285729

    申请日:2002-11-01

    IPC分类号: H01L2128

    摘要: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.18 &mgr;m silicon-only CMOS integrated circuits.

    摘要翻译: 形成GaAs / Ge on Si CMOS集成电路,通过利用N沟道器件中的GaAs的高电子迁移率和P沟道器件中的Ge的高空穴迁移率来提高晶体管开关(传播)延迟。 在硅基底上形成半绝缘(未掺杂的)GaAs层,以提供缓冲层,从而消除闩锁的可能性。 然后在半绝缘GaAs层上形成GaAs和Ge阱,通过标准热氧化物和/或可流动氧化物(HSQ)电隔离。 分别在GaAs和Ge阱中形成N沟道MOS器件和P沟道MOS器件,并互连形成集成电路。 用于两个阱中的器件的栅极可以是多晶硅,而栅极氧化物优选用于N沟道器件的氧化镓和用于P沟道器件的二氧化硅。 最小器件特征尺寸可以为0.5μm,以避免热载流子劣化,同时仍然实现超过0.18μm的仅硅CMOS集成电路的性能提高。

    Nanotube-based high energy material and method
    94.
    发明授权
    Nanotube-based high energy material and method 有权
    基于纳米管的高能材料及方法

    公开(公告)号:US06280697B1

    公开(公告)日:2001-08-28

    申请号:US09259307

    申请日:1999-03-01

    申请人: Otto Z. Zhou Bo Gao

    发明人: Otto Z. Zhou Bo Gao

    IPC分类号: C01B3100

    摘要: A carbon-based material containing an allotrope of carbon, such as single-walled carbon nanotubes, is capable of accepting and intercalated alkali metal. The material exhibits a reversible capacity ranging from approximately 650 mAh/g-1,000 mAh/g. The high capacity of the material makes it attractive for a number of applications, such as a battery electrode material. A method of producing a single-walled carbon nanotube material includes purifying an as-recovered nanotube material, and depositing the purified material onto a conductive substrate. The coated substrate is incorporated into an electrochemical cell, an its ability to accept intercalated materials, such as an alkali metal (e.g.—lithium) is measured.

    摘要翻译: 含有诸如单壁碳纳米管的碳同素异形体的碳基材料能够接受和插入碱金属。 该材料具有约650mAh / g-1,000mAh / g的可逆容量。 该材料的高容量使其对许多应用(例如电池电极材料)具有吸引力。 制造单壁碳纳米管材料的方法包括纯化回收的纳米管材料,以及将纯化的材料沉积到导电基材上。 将涂覆的基底并入电化学电池中,测量其接受插层材料(例如碱金属(例如锂))的能力。