公开(公告)号：US5658815A

公开(公告)日：1997-08-19

申请号：US581787

申请日：1996-01-02

Applicant: Chang-Jae Lee ,  Tae Gak Kim

Inventor： Chang-Jae Lee ,  Tae Gak Kim

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/6659 ,  H01L21/28105 ,  H01L21/28114 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7836

Abstract: A gate-drain overlapped device, comprising: a first conductive type substrate; a gate insulating film formed on the substrate; a gate comprising a gate conductive line patterned on the gate insulating film, and a conductive layer coated on the gate conductive line and extending to a predetermined length on the gate insulating film; and a drain/source region comprising a second conductive type low density diffusion region in the substrate below the extending area of the conductive layer and a second conductive type high density diffusion region in contact with the low density diffusion region in the substrate, which is significantly improved in the resistance of a polysilicon gate conductive line and in uniform electrical properties.

Abstract translation: 一种栅极 - 漏极重叠器件，包括：第一导电型衬底; 形成在基板上的栅极绝缘膜; 栅极，其包括在栅极绝缘膜上图案化的栅极导电线，以及涂覆在栅极导电线上并延伸到栅极绝缘膜上的预定长度的导电层; 以及漏极/源极区域，其在所述基板的所述导电层的延伸区域的下方具有第二导电型低密度扩散区域，以及与所述基板中的低密度扩散区域接触的第二导电型高密度扩散区域， 提高了多晶硅栅极导电线的电阻和均匀的电性能。

公开(公告)号：US5527719A

公开(公告)日：1996-06-18

申请号：US357950

申请日：1994-12-16

Applicant: Gum-Jin Park ,  Chang-Jae Lee ,  Won-Hyuk Lee

Inventor： Gum-Jin Park ,  Chang-Jae Lee ,  Won-Hyuk Lee

IPC: H01L21/266 ,  H01L21/336 ,  H01L21/469 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/266 ,  Y10S438/944

Abstract: A process for formation of an MOS semiconductor device having an LDD structure is disclosed, which may include the steps of: forming an active region and an isolation region on a semiconductor substrate; forming a first insulating layer on the surface of the substrate; forming a gate electrode on the first insulating layer in the active region; foxing a layer of a heat sensitive fluid material on the gate electrode; carrying out a first ion implantation into the substrate; carrying out a first heat treatment on the heat sensitive layer; carrying out a second ion implantation into the substrate; removing the residual fluid material; forming a second insulating layer on the whole surface of the wafer; and carrying out a second heat treatment on the wafer.

Abstract translation: 公开了一种用于形成具有LDD结构的MOS半导体器件的工艺，其可以包括以下步骤：在半导体衬底上形成有源区和隔离区; 在所述基板的表面上形成第一绝缘层; 在有源区中的第一绝缘层上形成栅电极; 在栅极电极上缠绕一层热敏流体材料; 对衬底进行第一离子注入; 对热敏层进行第一次热处理; 对基片进行第二离子注入; 去除残留的流体物质; 在晶片的整个表面上形成第二绝缘层; 并在晶片上进行第二次热处理。