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91.发明申请公开(公告)号：US20240420642A1
公开(公告)日：2024-12-19
申请号：US17771594
申请日：2020-11-24
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
Abstract: A shift register circuit includes an input sub-circuit, an output sub-circuit, a control sub-circuit and a compensation sub-circuit. The input sub-circuit is configured to, under control of a first input signal received at a first input signal terminal, transmit the first input signal to a pull-up node. The output sub-circuit is configured to transmit a first clock signal received at a first clock signal terminal to a first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal received at a first control signal terminal. The compensation sub-circuit is configured to transmit a voltage at a seventh node to the pull-up node under control of a seventh clock signal received at a seventh clock signal terminal.
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公开(公告)号：US20240395198A1
公开(公告)日：2024-11-28
申请号：US18262121
申请日：2022-05-30
Inventor： Liu WU , Xuehuan FENG , Yongqian LI
IPC: G09G3/3233 , G11C19/28
Abstract: A pixel circuit includes: a driving sub-circuit, a sensing sub-circuit, a light-emitting control sub-circuit, a sensing control sub-circuit, a light-emitting device and a sensing terminal. The driving sub-circuit includes a first terminal and a second terminal coupled to the light-emitting device, and is configured to write a data signal into the driving sub-circuit in response to a first scan signal and control an electrical signal flowing through the driving sub-circuit according to the data signal. The sensing sub-circuit is configured to connect the second terminal to the sensing terminal in response to a second scan signal. The light-emitting control sub-circuit is configured to connect a first voltage terminal to the first terminal in response to a light-emitting control signal. The sensing control sub-circuit is configured to connect a second voltage terminal to the first terminal in response to a sensing control signal provided by a sensing control terminal.
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公开(公告)号：US12154494B2
公开(公告)日：2024-11-26
申请号：US17772955
申请日：2021-05-13
Inventor： Meng Li , Yongqian Li , Chen Xu , Jingquan Wang , Dacheng Zhang , Yu Wang , Zhidong Yuan , Zhenhua Qiu
IPC: G09G3/3225 , H10K59/131
Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, a plurality of pixels, a plurality of gate lines and a plurality of data lines, wherein the base substrate has a plurality of transparent regions and a plurality of display regions; the pixels are on the base substrate and within the display regions; each pixel includes a plurality of sub pixels; the sub pixels of each pixel are divided into two rows of sub pixels; the gate lines and the data lines are on the base substrate; the sub pixels of a first pixel are connected with the same gate line; the gate line connected with the sub pixels of the first pixel is between the two rows of sub pixels of the first pixel; and the first pixel is any one of the plurality of pixels.
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公开(公告)号：US20240371328A1
公开(公告)日：2024-11-07
申请号：US18031560
申请日：2022-05-24
Inventor： Xuehuan FENG , Dacheng ZHANG
IPC: G09G3/3266 , G11C19/28
Abstract: The present disclosure provides shift register unit, including: sensing control circuit connected to sensing signal input terminal, random signal input terminal, and sensing control node, and configured to write signal provided by sensing signal input terminal to sensing control node in response to active level signal provided by random signal input terminal; first sensing input circuit connected to clock control signal input terminal, sensing control node, and first pull-up node, and configured to write signal provided by clock control signal input terminal to first pull-up node only in response to active level signal at sensing control node; and first driving output circuit connected to first pull-up node, first driving clock signal input terminal, and first driving signal output terminal, and configured to write signal provided by first driving clock signal input terminal to first driving signal output terminal in response to active level signal at first pull-up node.
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公开(公告)号：US20240296793A1
公开(公告)日：2024-09-05
申请号：US18026827
申请日：2022-06-14
Inventor： Can YUAN , Yongqian LI , Zhidong YUAN
IPC: G09G3/3233 , H10K59/131
CPC classification number: G09G3/3233 , H10K59/131 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08
Abstract: Provided is a display panel. The display panel includes: a substrate; a plurality of first control lines and a plurality of second control lines on a side of the substrate; and a plurality of subpixels arranged in an array on the side of the substrate, wherein at least two of the plurality of subpixels share a first node; wherein the subpixel includes a first circuit and a second circuit, the first circuit and the second circuit being configured to control a voltage at the first node in response to a first control signal and a second control signal; wherein in the display panel, a sum of a number of the plurality of first control lines and a number of the plurality of second control lines is less than or equal to a number of the subpixels in a column direction.
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Patent Agency Ranking
公开(公告)号：US20240257712A1
公开(公告)日：2024-08-01
申请号：US18005017
申请日：2021-08-20
Inventor： Xuehuan FENG , Yongqian LI
CPC classification number: G09G3/32 , G11C19/28 , G09G2310/0267 , G09G2310/0286 , G09G2330/021
Abstract: A shift resister includes a first scan unit and a black insertion circuit. The first scan unit includes a first input circuit and a first output circuit. The first input circuit is configured to transmit a display input signal to a first pull-up node. The first output circuit is configured to, in a case where the first input circuit transmits the display input signal to the first pull-up node, transmit a first clock signal to a first scan signal terminal. The black insertion circuit is configured to transmit a black insertion input signal to the first pull-up node. The first output circuit is further configured to, in a case where the black insertion circuit transmits the black insertion input signal to the first pull-up node, transmit the first clock signal to the first scan signal terminal.
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公开(公告)号：US12051386B2
公开(公告)日：2024-07-30
申请号：US17770250
申请日：2021-04-15
Inventor： Xuehuan Feng , Yongqian Li
CPC classification number: G09G5/006 , G11C19/28 , G09G2310/0286 , G09G2310/08
Abstract: The present disclosure provides a shift register unit, a signal generation unit circuit, a driving method and a display device. The shift register unit includes a first node control circuit, a second node control circuit and an output circuit, the first node control circuit is used to control a potential of a first node; the second node control circuit controls a potential of a second node; the output circuit is used to control and maintain the potential of the first node and the potential of the second node, and control to connect the output terminal and the second clock signal terminal under the control of the potential of the first node, and control to connect the input terminal and the second voltage terminal under the control of the potential of the second node.
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公开(公告)号：US20240249679A1
公开(公告)日：2024-07-25
申请号：US18017052
申请日：2022-02-11
Inventor： Wenchao BAO , Xuehuan FENG , Pengfei YIN
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2300/0842 , G09G2310/08 , G09G2320/0247
Abstract: A display panel, a driving method thereof and a display apparatus, including: a plurality of sub-pixels. Each sub-pixel includes a pixel circuit, and the pixel circuit includes: a light-emitting device (L); a drive transistor (M0), configured to generate a drive current driving the light-emitting device (L) to emit light according to a data voltage at a light-emitting stage (T2); a voltage control circuit (10), coupled to the drive transistor (M0) and configured to input the data voltage into the drive transistor (M0) at a data writing stage (T1); and a black frame insertion control circuit (20), coupled to the drive transistor (M0) and configured to control the drive transistor (M0) to stop generating the drive current at a black frame insertion stage (T3) after the light-emitting stage (T2).
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公开(公告)号：US20240242680A1
公开(公告)日：2024-07-18
申请号：US18618413
申请日：2024-03-27
Inventor： Xuehuan FENG , Yongqian LI , Hao LIU
IPC: G09G3/3266 , G09G3/3225 , G11C19/28
CPC classification number: G09G3/3266 , G09G3/3225 , G11C19/28 , G09G2310/0286
Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, a leakage prevention circuit and a blanking input sub-circuit, wherein the first sub-circuit includes a first input circuit and a first output circuit; the second sub-circuit includes a second input circuit and a second output circuit; the leakage prevention circuit is configured to control a level of a leakage prevention node under control of the level of the first node, so as to turn off a circuit connected between the first node and the leakage prevention node; and the blanking input sub-circuit is connected to the first node and the second node, and is configured to receive a selection control signal and a first clock signal, and control the level of the first node and the level of the second node.
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公开(公告)号：US20240233644A1
公开(公告)日：2024-07-11
申请号：US18547182
申请日：2022-09-30
Inventor： Liu Wu , Can Yuan , Zhidong Yuan , Cheng Xu , Luke Ding , Yongqian Li , Xiuting Liu
IPC: G09G3/3233 , H10K59/131
CPC classification number: G09G3/3233 , H10K59/131 , G09G2300/0814 , G09G2300/0819 , G09G2300/0842 , G09G2310/0221 , G09G2310/04 , G09G2310/08 , G09G2330/021 , G09G2340/0435
Abstract: A display substrate, including: a plurality of partition control signal lines disposed on a base substrate; and a plurality of sub-pixels disposed on the base substrate, at least one of the sub-pixels includes a pixel circuit and a light emitting device. The pixel circuit includes a switch transistor, a first partition control transistor, a drive transistor and a first initialization transistor. The first partition control transistor is electrically connected to the switch transistor, the first initialization transistor, the drive transistor and at least one partition control signal line. The first partition control transistor is configured to: in response to a partition control signal on the partition control signal line, selectively transmit a received first initialization signal to a gate electrode of the drive transistor in an initialization phase, and selectively transmit a received data signal to the gate electrode of the drive transistor in a data writing phase.
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