公开(公告)号：US06522172B2

公开(公告)日：2003-02-18

申请号：US09812757

申请日：2001-03-20

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： H03K1903

CPC分类号： H03K3/356121 ,  H03K3/012

摘要： A circuit having a data input pin for receiving a data signal, a clock input for receiving a clock signal and having a low setup time and a zero hold time is comprised of an input stage for periodically connecting a sampling device to the data input pin in response to the clock signal. An evaluation stage, responsive to the clock signal, evaluates the charge collected by the device at a time the device is disconnected from the data input pin. The evaluation stage produces a signal representative of the sampled charge. An output stage, responsive to the clock signal and the produced signal, outputs a data signal representative of the sampled data signal. The circuit may have a single data path and a single charge accumulating device such that an output signal representative of the sampled data signal is available on either the rising or the falling edge of the clock signal. Alternatively, multiple data paths may be provided as well as multiple charge accumulating devices so that data signals representative of the sampled data may be output on both the rising and the falling edge of the clock signal. The circuit can be operated as either a latch or a register. A method of operating a data acquisition and retention circuit having a zero hold time and of the type useful for receiving signals from a high speed bus is also disclosed.

摘要翻译： 具有用于接收数据信号的数据输入引脚的电路，用于接收时钟信号并具有低建立时间和零保持时间的时钟输入包括用于将采样装置周期性地连接到数据输入引脚的输入级 响应时钟信号。 响应于时钟信号的评估阶段评估设备在与数据输入引脚断开连接时收集的电荷。 评估阶段产生代表采样电荷的信号。 响应于时钟信号和产生的信号的输出级输出表示采样数据信号的数据信号。 电路可以具有单个数据路径和单个电荷累积装置，使得表示采样数据信号的输出信号在时钟信号的上升沿或下降沿都可用。 或者，可以提供多个数据路径以及多个电荷累积装置，使得表示采样数据的数据信号可以在时钟信号的上升沿和下降沿两者上输出。 该电路可以作为锁存器或寄存器来操作。 还公开了一种操作具有零保持时间的数据采集和保持电路以及用于从高速总线接收信号的类型的方法。

公开(公告)号：US06480031B2

公开(公告)日：2002-11-12

申请号：US10056384

申请日：2002-01-24

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： H03K19096

CPC分类号： H03K3/356121 ,  H03K3/012

摘要： A circuit having a data pin, an input pin for receiving a clock signal and having a zero hold time, is comprised of a sampling transistor for collecting charge at the data pin during a setup time defined by the clock signal; a device for isolating the sampling transistor from the data pin in response to the clock signal; and an output stage for outputting a logic signal in response to the charge sampled by the sampling transistor and the clock signal. The circuit may have an inverter for producing the complement of the clock signal, and the device for isolating may include a multiplexer responsive to the clock signal and the complement of the clock signal. The circuit can be operated as either a latch or a register. A method of operating a data acquisition and retention circuit having a zero hold time is also disclosed.

摘要翻译： 具有数据引脚的电路，用于接收时钟信号并具有零保持时间的输入引脚包括用于在由时钟信号定义的建立时间期间在数据引脚处收集电荷的采样晶体管; 用于响应于时钟信号将采样晶体管与数据引脚隔离的装置; 以及输出级，用于响应于由采样晶体管采样的电荷和时钟信号而输出逻辑信号。 电路可以具有用于产生时钟信号的补码的反相器，并且用于隔离的装置可以包括响应于时钟信号和时钟信号的补码的多路复用器。 该电路可以作为锁存器或寄存器来操作。 还公开了具有零保持时间的操作数据采集和保持电路的方法。

公开(公告)号：US06438023B1

公开(公告)日：2002-08-20

申请号：US09652622

申请日：2000-08-31

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： G11C1100

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087

摘要： A double-edge triggered storage device is triggered by either the rising edge, the falling edge, or both edges of a clock signal, thus realizing a higher data rate. The double-edge triggered storage device incorporates cross-coupled, enabled inverters on the inputs, thereby realizing short and potentially negative setup time. Cross-coupled tri-state inverters on the outputs improve clock-to-data times. A precharge-evaluate method is used for storing and transferring data on both rising and falling edge transitions of the clock signal. Weak feedback inverters are optionally used to maintain the state of the storage device in the absence of a clock signal.

摘要翻译： 双边沿触发存储设备由时钟信号的上升沿，下降沿或两个边沿触发，从而实现更高的数据速率。 双边沿触发的存储设备在输入上集成了交叉耦合的使能的反相器，从而实现了短暂且潜在的负建立时间。 输出上的交叉耦合三态反相器可提高时钟到数据时间。 预充电评估方法用于在时钟信号的上升沿和下降沿转换上存储和传送数据。 弱反馈逆变器可选地用于在没有时钟信号的情况下维持存储设备的状态。

公开(公告)号：US06411124B1

公开(公告)日：2002-06-25

申请号：US09761602

申请日：2001-01-16

申请人： Andy L. Lee ,  Brian Johnson ,  Richard G. Cliff

发明人： Andy L. Lee ,  Brian Johnson ,  Richard G. Cliff

IPC分类号： H03K19177

摘要： A logic module for a programmable logic device includes shift register circuitry in addition to the conventional programmable memory cells and look-up table decoder or selection control circuitry. In one embodiment the selection control circuitry can access either the memory cells or the various stages of the shift register. The shift register stages, and preferably the master and slave latches of each shift register stage, are accessed in a Gray code order. All of the stages of the shift register are preferably clearable in parallel. The shift registers of two logic modules are preferably cascadable to facilitate providing longer shift registers. Clock circuitry may be provided to facilitate providing two clock signals that are the logical inverse of one another with a common enable signal.

公开(公告)号：US6019266A

公开(公告)日：2000-02-01

申请号：US910450

申请日：1997-08-05

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： B60R9/06 ,  B60R9/10

CPC分类号： B60R9/06 ,  B60R9/10 ,  Y10S224/924

摘要： An improved bicycle carrying device for affixation to a vehicle, either to the bumper of the vehicle or to a permanent trailer hitch. The device comprises transverse support members to which the bicycle wheels are secured, and an upright member with elongate slots therein, within which adjustable, movable retaining members are affixed. The movable retaining members are moved into position such that they abut and are secured to an upper structural member of the bicycle. Therefore, the bicycle is restrained against lateral movement both at an upper and a lower position, securing the bicycle even during transport.

摘要翻译： 一种改进的自行车承载装置，用于固定到车辆，或者到车辆的保险杠或永久拖车搭接。 该装置包括固定有自行车车轮的横向支撑构件以及其中具有细长槽的直立构件，其中可固定可移动的保持构件。 可移动的保持构件被移动到位置，使得它们抵接并固定到自行车的上部结构构件。 因此，自行车在上部和下部位置处被限制在横向移动，即使在运输期间也能够固定自行车。

公开(公告)号：US5920572A

公开(公告)日：1999-07-06

申请号：US585109

申请日：1996-01-11

申请人： Emanuel Washington ,  Mike Perkins ,  Brian Johnson ,  Stephen How ,  Nolan Daines ,  Tom Ayers ,  Keith Vertrees

发明人： Emanuel Washington ,  Mike Perkins ,  Brian Johnson ,  Stephen How ,  Nolan Daines ,  Tom Ayers ,  Keith Vertrees

IPC分类号： H04N21/418 ,  H04N21/426 ,  H04N21/43 ,  H04J3/12

CPC分类号： H04N21/4181 ,  H04N21/42607 ,  H04N21/42615 ,  H04N21/42692 ,  H04N21/4305

摘要： A transport stream decoder/demultiplexer is provided which includes a program clock recovery circuit for recovering a program clock from program clock reference (PCR) values contained in selected transport packets. A processor is provided for extracting elementary stream data from transport packets labeled with packet identification codes (PIDs) that are specified by a host processor. The processor separately stores the elementary stream data of each stream. A host processor interface is also provided for transferring data between an external host processor and the program clock recovery circuit. A memory manager may be provided for storing the data extracted by the processor for each elementary stream in a corresponding queue. The queues may be maintained by the memory manager in an external RAM. A descrambler interface may be provided for transferring scrambled data and data derived from conditional access information between the processor and an external descrambler. In addition, at least one elementary stream interface, such as a video interface or audio interface, may be provided for outputting extracted elementary stream data for a particular elementary stream from a corresponding queue. Furthermore, a high speed interface may be provided for outputting transport packet data prior to data extraction by the processor.

摘要翻译： 提供了一种传输流解码器/解复用器，其包括用于从包含在所选传输分组中的程序时钟参考（PCR）值恢复程序时钟的程序时钟恢复电路。 提供处理器，用于从由主机处理器指定的分组识别码（PID）标记的传输分组中提取基本流数据。 处理器分别存储每个流的基本流数据。 还提供主处理器接口用于在外部主机处理器和程序时钟恢复电路之间传送数据。 可以提供存储器管理器，用于将由处理器提取的每个基本流的数据存储在相应的队列中。 队列可以由外部RAM中的存储器管理器维护。 可以提供解扰器接口，用于在处理器和外部解扰器之间传送加密数据和从条件访问信息导出的数据。 此外，可以提供至少一个基本流接口，例如视频接口或音频接口，用于从相应的队列输出用于特定基本流的提取的基本流数据。 此外，可以提供高速接口以在处理器提取数据之前输出传输分组数据。

公开(公告)号：US5835493A

公开(公告)日：1998-11-10

申请号：US581916

申请日：1996-01-02

申请人： Mark Magee ,  Brian Johnson ,  Tom Lookabaugh ,  Nolan Daines

发明人： Mark Magee ,  Brian Johnson ,  Tom Lookabaugh ,  Nolan Daines

IPC分类号： H04N21/236 ,  H04N21/2362 ,  H04N21/238 ,  H04J3/24

CPC分类号： H04N21/23608 ,  H04N21/238 ,  H04N21/2362

摘要： A remultiplexer is disclosed for communicating plural programs. Each program comprises one or more elementary streams that are encoded in relation to a single common time base corresponding to the respective program. The communicated programs originate from plural input transport streams that each comprises plural transport packets. Each transport packet contains a packet identifier indicating the data contained therein. Within each transport stream, unique packet identifiers are assigned to each elementary stream of each program. The data of each elementary stream is only contained in transport packets having a corresponding packet identifier. Each input transport stream contains time stamps for reconstructing the single program time base corresponding to each program conveyed therein. The remultiplexer has a data link module which receives the plural input transport streams. The data link module also selectively extracts transport packets from the received input transport streams. The remultiplexer has a downstream bus on which the data link module sequentially transfers at least some of the extracted transport packets. The remultiplexer selects which of the extracted transport packets to transfer on the downstream message bus depending on the packet identifiers of the transport packets. The remultiplexer also has a scheduler which assembles the transport packets transferred on the downstream bus into a single output transport stream.

公开(公告)号：US5159593A

公开(公告)日：1992-10-27

申请号：US546647

申请日：1990-07-02

申请人： Thomas V. D'Amico ,  Brian Johnson ,  Theodore Saltzberg

发明人： Thomas V. D'Amico ,  Brian Johnson ,  Theodore Saltzberg

IPC分类号： H04W72/02 ,  H04W72/06

CPC分类号： H04W72/02 ,  H04W48/20 ,  H04W24/10 ,  H04W48/08 ,  H04W48/16 ,  H04W72/0446 ,  H04W72/082

摘要： A TDMA communication system (100) comprises a two-way subscriber unit (112') and at least two base stations (104b and 104c). The subscriber unit monitors the strengths of signals (114') received from the base stations. As the subscriber unit roams within the area serviced by the communication system, the received signal strength will vary as the subscriber unit moves nearer to or farther from the base station that is transmitting the call. When the subscriber unit moves out of the range of the base station, the subscriber unit determines, based on certain predetermined criteria, with which base station to communicate.

摘要翻译： TDMA通信系统（100）包括双向用户单元（112'）和至少两个基站（104b和104c）。 用户单元监视从基站接收的信号（114'）的强度。 当用户单元在由通信系统服务的区域内漫游时，接收到的信号强度将随着用户单元更接近或远离正在发送呼叫的基站移动而变化。 当用户单元移出基站的范围时，用户单元基于某些预定标准确定要与哪个基站通信。

公开(公告)号：US5025399A

公开(公告)日：1991-06-18

申请号：US248811

申请日：1988-09-23

申请人： Richard W. Wendt ,  Brian Johnson

发明人： Richard W. Wendt ,  Brian Johnson

IPC分类号： B41J3/01 ,  B41J2/485 ,  B41J3/407 ,  B41J5/30 ,  B41J21/00 ,  G06F3/12 ,  G06F9/30 ,  G06K1/12 ,  G06T11/60

CPC分类号： G06K1/121 ,  G06T11/60

摘要： An apparatus for printing graphics images on plastic cards comprises a computer, a graphics printer connected to the computer, and control means executing on the computer for supplying graphic images to said graphics printer. The control means parse commands from an input data stream by identifying a delimiter preceding each command. The control means create images to be printed on the plastic card in response to the commands. The control means combine the images into a composite image and supply the composite image to the graphics printer.

摘要翻译： 用于在塑料卡上打印图形图像的装置包括计算机，连接到计算机的图形打印机以及在计算机上执行以向所述图形打印机提供图形图像的控制装置。 控制装置通过识别每个命令之前的分隔符来解析来自输入数据流的命令。 控制装置根据命令创建要在塑料卡上打印的图像。 控制装置将图像组合成合成图像，并将合成图像提供给图形打印机。

公开(公告)号：US4839650A

公开(公告)日：1989-06-13

申请号：US204026

申请日：1988-06-08

申请人： John A. Geen ,  Brian Johnson

发明人： John A. Geen ,  Brian Johnson

IPC分类号： H03M1/00 ,  H04J3/10

CPC分类号： H04J3/10 ,  H03M1/0641 ,  H03M1/1225 ,  H03M1/1019

摘要： Analog-to-digital converters are subject to errors including the known half least significant bit quantization error and also bit weighting errors due to lack of an ideal binary relationship between the transition points of all the bits. The known statistical average error reduction method in which a relatively small dither component is added to the analog input signal can only fractionally reduce overall error and has little effect on bit weighting errors. Herein the analog signal is added to a dither signal, for example a ramp signal, which varies through half the peak to peak digitization range of the converter so that irrespective of the input signal all output signal bits, other than the most significant bit, are "on" for one half of the sampling period. The result is that all the less significant bit errors are cancelled leaving only the easily compensated most significant bit error. A random component can be added to the dither signal to reduce the quantization error.