摘要:
A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.