公开(公告)号：US20240304697A1

公开(公告)日：2024-09-12

申请号：US18380930

申请日：2023-10-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L29/49 ,  H01L21/28035 ,  H01L21/28061 ,  H01L21/2807 ,  H01L21/28525 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3178 ,  H01L23/53271 ,  H01L23/5329 ,  H01L29/401 ,  H01L29/4916 ,  H01L29/4941 ,  H01L21/76802 ,  H01L23/53276 ,  H01L29/4236

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and having a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer comprises germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.

公开(公告)号：US20240266423A1

公开(公告)日：2024-08-08

申请号：US18420600

申请日：2024-01-23

申请人： STMicroelectronics International N.V.

发明人： Benjamin MORILLON

IPC分类号： H01L29/747 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/304

CPC分类号： H01L29/747 ,  H01L21/02323 ,  H01L21/28035 ,  H01L29/66386 ,  H01L21/3043

摘要： The present disclosure concerns a method of forming an electronic power component inside and on top of a semiconductor substrate, comprising the following successive steps: a) forming of a peripheral groove in the semiconductor substrate on the side of a first surface of the semiconductor substrate; b) deposition of an oxygen-doped polysilicon layer, on top of and in contact with the bottom and the lateral walls of the peripheral groove and with the first surface of the semiconductor substrate; c) local deposition of a glass layer, on the oxygen-doped polysilicon layer, the glass layer extending in the peripheral groove and further extending over a portion of the first surface of the semiconductor substrate; and d) etching of the oxygen-doped polysilicon layer so that it extends on the first surface of the semiconductor substrate beyond the glass layer.

公开(公告)号：US11948981B2

公开(公告)日：2024-04-02

申请号：US17405406

申请日：2021-08-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/401 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78645

摘要： A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.

公开(公告)号：US20230269945A1

公开(公告)日：2023-08-24

申请号：US17888998

申请日：2022-08-16

申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation

发明人： Ning WANG ,  Kegang ZHANG

IPC分类号： H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L27/1157 ,  H01L21/28035 ,  H01L29/66833 ,  H01L21/0214

摘要： An embedded SONOS memory and a method for making the same. The method includes: forming a connecting layer on one side of a selection transistor polysilicon gate; forming a second silicon oxide layer and an ONO charge storage layer on the other side of the selection transistor polysilicon gate far away from the connecting layer; then forming a memory transistor polysilicon gate on the side of the second silicon oxide layer far away from the connecting layer, so as to obtain the selection transistor polysilicon gate and the memory transistor polysilicon gate in a back-to-back structure.

公开(公告)号：US20190109216A1

公开(公告)日：2019-04-11

申请号：US16149255

申请日：2018-10-02

申请人： Silergy Semiconductor Technology (Hangzhou) LTD

发明人： Jinyong Cai ,  Zhongping Liao

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/28 ,  H01L29/417 ,  H01L29/10 ,  H01L21/3213 ,  H01L29/49

CPC分类号： H01L29/66734 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32135 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/7813

摘要： A method of manufacturing a trench MOSFET can include: forming an epitaxial semiconductor layer having a first doping type on a semiconductor substrate; forming a trench extending from a first surface of the epitaxial semiconductor layer to an internal portion of the epitaxial semiconductor layer; forming a first insulating layer and a shield conductor occupying a lower portion of said trench, where the first insulating layer is located on a lower sidewall surface and a bottom surface of the trench and separates the shield conductor from the epitaxial semiconductor layer; forming a second insulating layer covering a top surface of said shield conductor, where the second insulating layer is patterned by using a hard mask; forming a gate dielectric layer and a gate conductor occupying an upper portion of the trench; and forming a body region, a source region, and a drain electrode.

公开(公告)号：US09972539B2

公开(公告)日：2018-05-15

申请号：US15475097

申请日：2017-03-30

申请人： UNITED MICROELECTRONICS CORP.

发明人： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L21/823456 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

摘要： A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

公开(公告)号：US09964516B2

公开(公告)日：2018-05-08

申请号：US15427846

申请日：2017-02-08

申请人： NXP USA, Inc.

发明人： Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza ,  Md M. Hoque ,  John M. McKenna

IPC分类号： G11C16/04 ,  G01N27/414 ,  H01L29/788 ,  H01L49/02 ,  H01L21/28 ,  G05F1/575

CPC分类号： G01N27/4148 ,  G05F1/575 ,  G11C16/0416 ,  H01L21/28035 ,  H01L23/5223 ,  H01L27/11526 ,  H01L27/11558 ,  H01L28/40 ,  H01L28/60 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

公开(公告)号：US20180097005A1

公开(公告)日：2018-04-05

申请号：US15832636

申请日：2017-12-05

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/102 ,  H01L29/66 ,  H01L21/321 ,  H01L21/324 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/45

CPC分类号： H01L27/1027 ,  G11C11/39 ,  H01L21/28035 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76224 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/1016 ,  H01L29/102 ,  H01L29/16 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/749

摘要： Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.

公开(公告)号：US20180076297A1

公开(公告)日：2018-03-15

申请号：US15641455

申请日：2017-07-05

申请人： SUPER GROUP SEMICONDUCTOR CO., LTD.

发明人： HSIU-WEN HSU

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28158 ,  H01L29/0646 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7813

摘要： A trench power semiconductor device and a manufacturing method thereof are provided. The trench power semiconductor device includes a substrate, an epitaxial layer disposed on the substrate, and a gate structure. The epitaxial layer has at least one trench formed therein, and the gate structure is disposed in the trench. A gate structure includes a lower doped region and an upper doped region disposed above the lower doped region to form a PN junction. The concentration of the impurity decreases along a direction from a peripheral portion of the upper doped region toward a central portion of the upper doped region.

公开(公告)号：US20180068856A1

公开(公告)日：2018-03-08

申请号：US15643341

申请日：2017-07-06

申请人： Renesas Electronics Corporation

发明人： Kazuya HORIE ,  Katsuhiro UCHIMURA ,  Kazuhiro TOI ,  Masakazu NAKANO

IPC分类号： H01L21/28 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/283 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L21/324 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/3065 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/32155 ,  H01L29/66 ,  H01L29/66659 ,  H01L29/66727 ,  H01L29/66734

摘要： In manufacturing a trench type MOSFET, reliability of a semiconductor device is prevented from being degraded due to a short circuit or lowering of withstand voltage between a trench gate electrode and a source region.To achieve the above, poly-silicon films are formed inside a trench in a main surface of a semiconductor substrate and over the semiconductor substrate. Further, phosphorus is thermally diffused into each poly-silicon film from a phosphorous film over an upper surface of the poly-silicon film. Still further, a silicon oxide film formed in a surface layer of the poly-silicon film by the thermal diffusion process is removed by a first dry etching process using a fluorocarbon gas or a hydroxy-fluorocarbon gas. Then, by performing a second dry etching process using a Cl2 gas etc., an insulating film is exposed and, thereby, a trench gate electrode including the poly-silicon film is formed.