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公开(公告)号：US06720631B2
公开(公告)日：2004-04-13
申请号：US08954430
申请日：1997-10-20
IPC分类号： H01L2976
CPC分类号： H01L29/0847 , H01L29/42368 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , Y10S257/90
摘要： A transistor comprising a deposited dual-layer spacer structure and method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.
摘要翻译： 一种包括沉积的双层间隔结构和制造方法的晶体管。 多晶硅层沉积在栅极电介质上，随后被蚀刻以形成晶体管的多晶硅栅电极。 接下来，在栅电极的表面上沉积氧化物，随后沉积第二介电层。 然后通过使用蚀刻第二介电层的基本上各向异性的蚀刻比蚀刻氧化物更快地蚀刻回第二介电层而形成与栅电极相邻的间隔物。
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2.发明授权
公开(公告)号：US6017819A
公开(公告)日：2000-01-25
申请号：US970715
申请日：1997-11-14
IPC分类号： H01L21/027 , H01L21/28 , H01L29/49 , H01L21/3213 , H01L21/324 , H01L21/441
CPC分类号： H01L29/4925 , H01L21/0276 , H01L21/28035 , H01L21/28123 , Y10S438/952
摘要： A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.
摘要翻译： 在金属氧化物半导体（MOS）器件的制造中，用于在门电极的图形化中改善线宽控制的多晶硅/非晶硅复合层。 在集成电路中形成复合多晶硅/非晶硅栅极为器件提供了多晶硅栅极的电性能和掺杂质量，并且还为器件提供非晶硅栅极的平滑度，从而改善栅极图案化过程中线的定义。
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公开(公告)号：US5633202A
公开(公告)日：1997-05-27
申请号：US660734
申请日：1996-06-06
IPC分类号： H01L21/318 , H01L21/336 , H01L21/44 , H01L21/02
CPC分类号： H01L29/6659 , H01L21/3185 , H01L29/665 , H01L29/7843 , Y10S438/954
摘要： An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8.times.10.sup.9 dynes/cm.sup.-2 and -3.times.10.sup.10 dynes/cm.sup.-2. The insulating layer can further comprise a doped oxide layer under the nitride layer and can further comprise an interlevel dielectric layer over the nitride layer. Moreover, the nitride layer can be formed by bringing the temperature in a chemical vapor deposition reactor to below 550 degrees Celsius, placing the substrate into the reactor at the temperature, and forming the nitride layer on the substrate. Alternatively, the nitride layer can be formed by pushing the substrate into a chemical vapor deposition reactor at a speed greater than 300 millimeters per minute, and forming the nitride layer on the substrate.
摘要翻译： 描述半导体器件中的绝缘层和用于形成绝缘层的工艺。 绝缘层包括在衬底上的氮化物层，其残余应力在-8x109达因/厘米-2和-3×10 10达因/厘米-2之间。 绝缘层还可以包括在氮化物层下方的掺杂氧化物层，并且还可以包括在氮化物层上的层间电介质层。 此外，可以通过使化学气相沉积反应器中的温度低于550摄氏度，将衬底置于反应器中并在衬底上形成氮化物层来形成氮化物层。 或者，可以通过以大于300毫米/分钟的速度将衬底推入化学气相沉积反应器中并在衬底上形成氮化物层来形成氮化物层。
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公开(公告)号：US06703672B1
公开(公告)日：2004-03-09
申请号：US08917796
申请日：1997-08-25
IPC分类号： H01L2976
CPC分类号： H01L29/4925 , H01L21/0276 , H01L21/28035 , H01L21/28123 , Y10S438/952
摘要： A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.
摘要翻译： 在金属氧化物半导体（MOS）器件的制造中，用于在门电极的图形化中改善线宽控制的多晶硅/非晶硅复合层。 在集成电路中形成复合多晶硅/非晶硅栅极为器件提供了多晶硅栅极的电性能和掺杂质量，并且还为器件提供非晶硅栅极的平滑度，从而改善栅极图案化过程中线的定义。
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公开(公告)号：US5911111A
公开(公告)日：1999-06-08
申请号：US944041
申请日：1997-09-02
IPC分类号： H01L21/28 , H01L21/321 , H01L21/44
CPC分类号： H01L21/3212 , H01L21/28123
摘要： A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance metal oxide semiconductor (MOS) devices. The addition of a short silicon polish step, after deposition and before patterning of a polysilicon layer reduces the non-planarity normally associated with polysilicon. Polysilicon polishing removes the surface roughness in the polysilicon layer caused by the grain structure of polysilicon and the surface roughness due to the replication of the underlying topography of the isolation and substrate regions. The described method for removal of both types of surface roughness leaves the polysilicon layer planarized without increasing the defect level already associated with the manufacture of high performance MOS devices.
摘要翻译： 在制造高性能金属氧化物半导体（MOS）器件中使用标准图案化技术的多晶硅栅极图案化改进的抛光工艺。 在沉积之后和在多晶硅层的图案化之前添加短硅抛光步骤减少了通常与多晶硅相关的非平面性。 多晶硅抛光消除由多晶硅的晶粒结构引起的多晶硅层中的表面粗糙度以及由于隔离和衬底区域的底部形貌的复制所引起的表面粗糙度。 所描述的用于去除两种类型的表面粗糙度的方法使多晶硅层平坦化，而不增加已经与高性能MOS器件的制造相关联的缺陷水平。
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6.发明授权公开(公告)号：US06274913B1
公开(公告)日：2001-08-14
申请号：US09166818
申请日：1998-10-05
IPC分类号： H01L2976
CPC分类号： H01L29/66643 , H01L21/76264 , H01L21/76283 , H01L27/1203 , H01L29/0895 , H01L29/66636
摘要： Microelectronic structures embodying the present invention include a silicon pillar contiguous with a bulk semiconductor, the pillar being surrounded by a shallow trench isolation insulator, which has been recessed to receive polysilicon and a superjacent layer of silicon deposited thereon. Source and drain (S/D) terminals are formed in the silicon of the recessed portions of the shallow trench isolation insulator. In this way the S/D terminals are substantially isolated from the body, thereby substantially reducing both parasitic junction capacitance and junction leakage currents. Isolation of S/D terminals in this way also reduces the degradation of effective channel length that can otherwise occur in MOSFETs.
摘要翻译： 体现本发明的微电子结构包括与体半导体邻接的硅柱，所述柱被浅沟槽隔离绝缘体包围，所述浅沟槽隔离绝缘体已被凹入以接收多晶硅和沉积在其上的硅的上层。 源极和漏极（S / D）端子形成在浅沟槽隔离绝缘体的凹陷部分的硅中。 以这种方式，S / D端子与本体基本隔离，从而大大减少寄生结电容和结漏电流。 以这种方式隔离S / D端子也可以降低有效沟道长度的劣化，否则可能发生在MOSFET中。
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7.发明授权Method of making a transistor having a deposited dual-layer spacer structure 失效制造具有沉积的双层间隔结构的晶体管的方法
公开(公告)号：US5714413A
公开(公告)日：1998-02-03
申请号：US570726
申请日：1995-12-11
IPC分类号： H01L21/336 , H01L29/08 , H01L29/423 , H01L29/78
CPC分类号： H01L29/6656 , H01L29/0847 , H01L29/42368 , H01L29/6659 , H01L29/66636 , H01L29/7833 , Y10S257/90
摘要： A transistor comprising a deposited dual-layer spacer structure and method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.
摘要翻译： 一种晶体管，包括沉积的双层间隔结构和制造方法。 多晶硅层沉积在栅极电介质上，随后被蚀刻以形成晶体管的多晶硅栅电极。 接下来，在栅电极的表面上沉积氧化物，随后沉积第二介电层。 然后通过使用蚀刻第二介电层的基本上各向异性的蚀刻比蚀刻氧化物更快地蚀刻回第二介电层而形成与栅电极相邻的间隔物。
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8.发明授权公开(公告)号：US06380010B2
公开(公告)日：2002-04-30
申请号：US09887903
申请日：2001-06-21
IPC分类号： H01L2184
CPC分类号： H01L29/66643 , H01L21/76264 , H01L21/76283 , H01L27/1203 , H01L29/0895 , H01L29/66636
摘要： Microelectronic structures embodying the present invention include a silicon pillar contiguous with a bulk semiconductor, the pillar being surrounded by a shallow trench isolation insulator, which has been recessed to receive polysilicon and a superjacent layer of silicon deposited thereon. Source and drain (S/D) terminals are formed in the silicon of the recessed portions of the shallow trench isolation insulator. In this way the S/D terminals are substantially isolated from the body, thereby substantially reducing both parasitic junction capacitance and junction leakage currents. Isolation of S/D terminals in this way also reduces the degradation of effective channel length that can otherwise occur in MOSFETs.
摘要翻译： 体现本发明的微电子结构包括与体半导体邻接的硅柱，所述柱被浅沟槽隔离绝缘体包围，所述浅沟槽隔离绝缘体已被凹入以接收多晶硅和沉积在其上的硅的上层。 源极和漏极（S / D）端子形成在浅沟槽隔离绝缘体的凹陷部分的硅中。 以这种方式，S / D端子与本体基本隔离，从而大大减少寄生结电容和结漏电流。 以这种方式隔离S / D端子也可以降低有效沟道长度的劣化，否则可能发生在MOSFET中。
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公开(公告)号：US6046494A
公开(公告)日：2000-04-04
申请号：US791867
申请日：1997-01-31
IPC分类号： H01L21/318 , H01L21/336 , H01L23/58 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6659 , H01L21/3185 , H01L29/665 , H01L29/7843 , Y10S438/954
摘要： An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8.times.10.sup.9 dynes/cm.sup.-2 and -3.times.10.sup.10 dynes/cm.sup.-2. The insulating layer can further comprise a doped oxide layer under the nitride layer and can further comprise an interlevel dielectric layer over the nitride layer. Moreover, the nitride layer can be formed by bringing the temperature in a chemical vapor deposition reactor to below 550 degrees Celsius, placing the substrate into the reactor at the temperature, and forming the nitride layer on the substrate. Alternatively, the nitride layer can be formed by pushing the substrate into a chemical vapor deposition reactor at a speed greater than 300 millimeters per minute, and forming the nitride layer on the substrate.
摘要翻译： 描述半导体器件中的绝缘层和用于形成绝缘层的工艺。 绝缘层包括在衬底上的氮化物层，其残余应力在-8x109达因/厘米-2和-3×10 10达因/厘米-2之间。 绝缘层还可以包括在氮化物层下方的掺杂氧化物层，并且还可以包括在氮化物层上的层间电介质层。 此外，可以通过使化学气相沉积反应器中的温度低于550摄氏度，将衬底置于反应器中并在衬底上形成氮化物层来形成氮化物层。 或者，可以通过以大于300毫米/分钟的速度将衬底推入化学气相沉积反应器中并在衬底上形成氮化物层来形成氮化物层。
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10.发明授权
公开(公告)号：US5891809A
公开(公告)日：1999-04-06
申请号：US536653
申请日：1995-09-29
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/762 , H01L29/51 , H01L21/31
CPC分类号： H01L21/28185 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L21/31662 , H01L21/76235 , H01L29/518 , H01L29/6656 , H01L29/6659
摘要： A method of forming a thin, robust nitrided oxide layer. The process results in a manufacturable, uniform, low-defect density, reliable nitrided oxide that may be used as a gate dielectric, as a portion of a spacer, or as a portion of a trench isolation. First, a substrate is oxidized in a chlorinated dry oxidation followed by a low temperature pyrogenic steam oxidation. Next, a low temperature ammonia anneal is performed, followed by a high temperature anneal in an inert ambient.
摘要翻译： 形成薄而坚固的氮化氧化物层的方法。 该方法产生可制造，均匀，低缺陷密度，可靠的氮化氧化物，其可以用作栅极电介质，作为间隔物的一部分，或者作为沟槽隔离的一部分。 首先，将基板在氯化干燥氧化中氧化，然后进行低温热解蒸汽氧化。 接下来，进行低温氨退火，随后在惰性环境中进行高温退火。
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