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91.发明申请公开(公告)号：US20170302765A1
公开(公告)日：2017-10-19
申请号：US15483911
申请日：2017-04-10
Inventor： Jae-Young LEE , Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Heung-Mook KIM
CPC classification number: H04L69/324 , H04L1/0041 , H04L1/0045 , H04L1/0071 , H04L1/0075 , H04L5/0026 , H04L27/2608 , H04L27/2613 , H04L27/2626 , H04L27/2628 , H04L27/2647 , H04L27/3488
Abstract: An apparatus and method for generating a broadcast signal frame for signaling a time interleaving mode are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing time interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling a time interleaving mode corresponding to the time interleaver for each of physical layer pipes (PLPs).
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公开(公告)号：US20170294987A1
公开(公告)日：2017-10-12
申请号：US15532065
申请日：2016-03-25
Inventor： Sun-Hyoung KWON , Jae-Young LEE , Sung-Ik PARK , Bo-Mi LIM , Heung-Mook KIM , Jin-Hyuk SONG
CPC classification number: H04L1/0071 , H04L1/00 , H04L1/0058 , H04L1/007 , H04L5/0053 , H04L27/26 , H04L27/2602 , H04L27/3488 , H04L2001/0093 , H04W72/005 , Y02D70/00
Abstract: An apparatus and method for broadcast signal frame using a boundary between Physical Layer Pipes (PLPs) of a core layer are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and a boundary between the time interleaver groups is a boundary between Physical Layer Pipes (PLPs) of a core layer corresponding to the core layer signal.
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公开(公告)号：US20170187394A1
公开(公告)日：2017-06-29
申请号：US15423539
申请日：2017-02-02
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1148 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
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公开(公告)号：US20170149455A1
公开(公告)日：2017-05-25
申请号：US15425734
申请日：2017-02-06
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , G06F11/1076 , H03M13/1102 , H03M13/1148 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
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公开(公告)号：US20170149453A1
公开(公告)日：2017-05-25
申请号：US15423496
申请日：2017-02-02
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/036 , H03M13/1148 , H03M13/116 , H03M13/1165 , H03M13/255 , H03M13/616 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
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Patent Agency Ranking
公开(公告)号：US20170117923A1
公开(公告)日：2017-04-27
申请号：US15402107
申请日：2017-01-09
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2757 , H03M13/2778 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L27/20 , H04L27/3416
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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97.发明申请APPARATUS FOR TRANSMITTING/RECEIVING BROADCASTING SIGNAL USING COMBINATION MODE OF LAYERED DIVISION MULTIPLEXING AND CHANNEL BONDING, AND METHOD THEREOF 审中-公开使用层叠多路复用和通道绑定的组合模式发送/接收广播信号的装置及其方法公开(公告)号：US20170019207A1
公开(公告)日：2017-01-19
申请号：US15212109
申请日：2016-07-15
Inventor： Sung-Ik PARK , Jae-Young LEE , Sun-Hyoung KWON , Heung-Mook KIM , Bo-Mi LIM , David GOMEZ-BARQUERO , Eduardo GARRO , Jordi Joan GIMENEZ
CPC classification number: H04L1/0003 , H04J11/004 , H04L1/0048 , H04L1/0071 , H04L5/0007 , H04L27/2627 , H04L27/2649 , H04L27/345 , H04L27/3488 , H04L2001/0093 , H04W52/42
Abstract: An apparatus for transmitting broadcast signal according to the present invention includes an enhanced layer stream partitioner configured to generate first and second enhanced layer partitioned signals by partitioning an enhanced layer stream; first and second combiners configured to generate a first multiplexed signal corresponding to the first enhanced layer partitioned signal and a second multiplexed signal corresponding to the second enhanced layer partitioned signal; first and second power normalizers configured to reduce powers of the first multiplexed signal and the second multiplexed signal; first and second time interleavers configured to generate a first time-interleaved signal corresponding to the first enhanced layer partitioned signal and a second time-interleaved signal corresponding to the second enhanced layer partitioned signal; and first and second OFDM transmitters configured to transmit signals corresponding to the first time-interleaved signal and the second time-interleaved signal using an OFDM communication scheme.
Abstract translation: 根据本发明的用于发送广播信号的装置包括被配置为通过分割增强层流来生成第一和第二增强层分割信号的增强层流分割器; 第一和第二组合器，被配置为产生对应于第一增强层分割信号的第一复用信号和对应于第二增强层分割信号的第二复用信号; 第一和第二功率归一化器被配置为减少第一复用信号和第二复用信号的功率; 第一和第二时间交织器被配置为生成对应于第一增强层分割信号的第一时间交织信号和对应于第二增强层分割信号的第二时间交织信号; 以及第一和第二OFDM发射机，被配置为使用OFDM通信方案发送对应于第一时间交织信号和第二时间交织信号的信号。
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98.发明申请LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME 审中-公开低密度奇偶校验编码器的长度为64800，编码速率为2/15，低密度奇偶校验编码方法使用该编码方法公开(公告)号：US20170012645A1
公开(公告)日：2017-01-12
申请号：US15271169
申请日：2016-09-20
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1177 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/616 , H03M13/6552 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为64800，码率为2/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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99.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为16200，编码速率为4/15和64符号映射，以及使用相同的位交互方法公开(公告)号：US20160241271A1
公开(公告)日：2016-08-18
申请号：US14719254
申请日：2015-05-21
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2767 , H03M13/1105 , H04L1/0041 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为16200且码率为4/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于64符号映射的调制器。
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100.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为16200，编码速率为4/15和256符号映射，以及使用相同的位交互方法公开(公告)号：US20160241269A1
公开(公告)日：2016-08-18
申请号：US14718839
申请日：2015-05-21
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/1165 , H03M13/255 , H03M13/2778
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为16200且码率为4/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于256符号映射的调制器。
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