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    METHOD AND APPARATUS FOR A PARAMETERIZED INTERLEAVER DESIGN PROCESS
    2.
    发明申请
    METHOD AND APPARATUS FOR A PARAMETERIZED INTERLEAVER DESIGN PROCESS 有权
    用于参数交互设计过程的方法和装置

    公开(公告)号：US20130318421A1

    公开(公告)日：2013-11-28

    申请号：US13955862

    申请日：2013-07-31

    申请人： Hughes Network Systems. LLC

    发明人： Rohit Iyer SESHADRI ,  Mustafa EROZ ,  Lin-Nan LEE

    IPC分类号： H03M13/27

    CPC分类号： H03M13/2767 ,  H03M13/275 ,  H03M13/276 ,  H03M13/2789

    摘要： A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations.

    摘要翻译： 提供了一种参数化的交织器设计过程，其优化了任何尺寸的交织器的设计，并且可以仅使用少量设计参数来完全指定。 根据参数化交织器设计处理，生成长度为N的交织器pi（i）。 定义了多个子鉴别掩码，并且将第一中间交织器置换分割成多个子组，其中子组的数量对应于子鉴别掩码的数量。 第一中间交织器置换的每个子组被划分成多个其他子组，并且每个子精确掩码被应用于第一中间交织器置换的对应子组的其他子组中的每一个，导致相应部分 第二中间交织器排列。 至少部分地基于第一和第二中间交织器排列来生成所产生的交织器pi（i）。

    Interleaver for iterative decoder
    5.
    发明授权
    Interleaver for iterative decoder 失效
    交织器用于迭代解码器

    公开(公告)号：US07360040B2

    公开(公告)日：2008-04-15

    申请号：US11231635

    申请日：2005-09-21

    申请人： Hiroshi Suzuki ,  Stephen Edward Krafft

    发明人： Hiroshi Suzuki ,  Stephen Edward Krafft

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： H04L1/005 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2785 ,  H03M13/2957 ,  H03M13/4161 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

    摘要： Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

    摘要翻译： 交织器用于迭代解码器。 存储器管理方案允许单平面/单端口存储器件由交织器使用。 该设计适用于执行迭代解码的软进软（SISO）解码器。 交织器可以在实现两个不同的SISO的通信设备中实现，这两个SISO协作地或在使用在功能上执行由两个不同的SISO实现执行的类似解码操作的单个SISO（在回收的实施例中）的通信设备内。 通过交织器使用单平面/单端口存储器件允许从许多角度大量节省：使用这种方法所需的交织器存储器和交织器模式存储器的尺寸都被削减了一半，并且可以节省成本 也可以实现，由于每个相应的交织器存储器仅在每隔一个周期读取，所以可以使用更便宜的较慢的存储器。

    Turbo code interleaver with near optimal performance
    6.
    发明申请
    Turbo code interleaver with near optimal performance 有权
    Turbo码交织器具有接近最佳性能

    公开(公告)号：US20080059727A1

    公开(公告)日：2008-03-06

    申请号：US11980916

    申请日：2007-10-31

    申请人： Mustafa Eroz ,  A. Hammons ,  Feng-Wen Sun

    发明人： Mustafa Eroz ,  A. Hammons ,  Feng-Wen Sun

    IPC分类号： G06F12/00

    CPC分类号： H03M13/271 ,  H03M13/2735 ,  H03M13/2746 ,  H03M13/276 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2789 ,  H03M13/2957

    摘要： A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

    摘要翻译： 公开了一种交织具有不同长度的索引数据块的方法。 该方法包括以下步骤：提供一组基本交错器，其包括索引数据的一个或多个排列的族，并具有可变长度; 基于所需的交织器长度L选择基本交织器之一; 并且使所选择的基本交织器适配以产生具有期望的交织器长度L的交织器。

    Interleaving/de-interleaving using compressed bit-mapping sequences
    8.
    发明申请
    Interleaving/de-interleaving using compressed bit-mapping sequences 有权

    公开(公告)号：US20060156094A1

    公开(公告)日：2006-07-13

    申请号：US11016643

    申请日：2004-12-17

    申请人： Dayong Chen

    发明人： Dayong Chen

    IPC分类号： G11C29/00

    CPC分类号： H03M13/6502 ,  H03M13/2703 ,  H03M13/2767

    摘要： A method of mapping input bit positions in an input sequence to output bit positions in an output sequence uses compressed mapping sequences stored in memory derived from a predetermined mapping function. The mapping function is decompressed into periodic component functions that are used to generate the compressed mapping sequences. Each compressed mapping sequence comprises a plurality of partial mapping values that represent one period of a corresponding component function or group of component functions. Partial mapping values are selected from each compressed mapping sequence based on a bit index of the current input bit and summed or otherwise combined to get an output index.