公开(公告)号：US06874109B1

公开(公告)日：2005-03-29

申请号：US09713662

申请日：2000-11-15

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

IPC分类号： G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

公开(公告)号：US5313469A

公开(公告)日：1994-05-17

申请号：US75629

申请日：1993-06-11

申请人： Saman Adham ,  Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab

发明人： Saman Adham ,  Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab

IPC分类号： G01R31/3183 ,  G01R31/28

CPC分类号： G01R31/318321

摘要： A self-testable digital integrator comprises binary adding apparatus and storage apparatus. The adding apparatus and the storage apparatus are functionally interconnected such that the storage apparatus feeds digital words to the adding apparatus for addition thereof and the adding apparatus feeds resulting digital words to the storage apparatus for storage thereof to perform a digital integration operation. The digital integrator further comprises a first combinational network responsive to a first state of a test mode signal to feed an external input signal to the adding apparatus for integration thereof, and responsive to a second state of the test mode signal to feed to the adding apparatus a test pattern signal derived from selected bias of the digital words fed from the adding apparatus to the storage apparatus. The digital integrator also comprises a second combinational network responsive to the second state of the test mode signal to feed back a carry-out bit of the adding apparatus to a carry-in port of the adding apparatus for test result compaction. The digital integrator optionally comprises a third combinational network responsive to the second state of the test mode signal to feed a carry-out bit of the adding apparatus to the first combinational network, the first combinational network being responsive to the second state of the test mode signal and to the carry-out bit to modify the test pattern signal. The self-testable digital integrator is particularly useful as a component of a digital decimator used to decimate Double Integration Sigma Delta modulation signals.

摘要翻译： 一种可自检的数字积分器包括二进制加法装置和存储装置。 所述添加装置和所述存储装置在功能上互连，使得所述存储装置将数字字馈送到所述添加装置以添加，并且所述添加装置将所生成的数字字馈送到所述存储装置以进行存储以进行数字集成操作。 数字积分器还包括响应于测试模式信号的第一状态的第一组合网络，以将外部输入信号馈送到加法装置以进行积分，并响应于测试模式信号的第二状态馈送到添加装置 从从加法装置馈送到存储装置的数字字的选定偏置导出的测试图案信号。 数字积分器还包括响应于测试模式信号的第二状态的第二组合网络，以将加法装置的进位位反馈到用于测试结果压缩的加法装置的进位端口。 数字积分器可选地包括响应于测试模式信号的第二状态的第三组合网络，以将加法装置的进位位馈送到第一组合网络，第一组合网络响应于测试模式的第二状态 信号和进位位修改测试码信号。 自检数字积分器作为用于抽取双积分Sigma Delta调制信号的数字抽取器的组件特别有用。

公开(公告)号：US20050015688A1

公开(公告)日：2005-01-20

申请号：US10911033

申请日：2004-08-03

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

IPC分类号： G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G11B20/20 ,  G06K5/04 ,  G11B5/00

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

摘要翻译： 公开了用于自动合成移相器的方法。 移相器包括用于消除驱动并行扫描链的伪随机测试图形发生器特征的结构依赖性的影响的电路。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

公开(公告)号：US06728901B1

公开(公告)日：2004-04-27

申请号：US09276474

申请日：1999-03-25

申请人： Janusz Rajski ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Jerzy Tyszer

IPC分类号： G06F1300

CPC分类号： G06F11/2221 ,  G01R31/318385 ,  G01R31/318547

摘要： An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Operating logic uses data paths of the processor core to implement the ABIST. In one embodiment, operating logic generates test patterns for the peripheral devices using the data paths of the processor core, loads the test patterns into the parallel scan registers of the peripheral devices, recovers test responses from the parallel scan registers, and compacts responses from the peripheral devices once again using the data paths of the processor core.

摘要翻译： 一种装置和方法提供了具有耦合到处理器核心的并行扫描寄存器的多个外围设备的算术内置自检（ABIST），全部在集成电路内。 操作逻辑使用处理器内核的数据路径实现ABIST。 在一个实施例中，操作逻辑使用处理器核心的数据路径为外围设备生成测试模式，将测试模式加载到外围设备的并行扫描寄存器，恢复来自并行扫描寄存器的测试响应，并压缩来自 外围设备再次使用处理器核心的数据路径。

公开(公告)号：US07805651B2

公开(公告)日：2010-09-28

申请号：US12633601

申请日：2009-12-08

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

IPC分类号： G01R31/28

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

摘要翻译： 公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

公开(公告)号：US07523372B2

公开(公告)日：2009-04-21

申请号：US11895845

申请日：2007-08-27

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

IPC分类号： G01R31/28

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

摘要翻译： 公开了用于自动合成移相器的方法。 移相器包括用于消除驱动并行扫描链的伪随机测试图形发生器特征的结构依赖性的影响的电路。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

公开(公告)号：US06954888B2

公开(公告)日：2005-10-11

申请号：US10777443

申请日：2004-02-10

申请人： Janusz Rajski ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Jerzy Tyszer

IPC分类号： G01R31/3185 ,  G06F11/267 ,  H02H3/05 ,  G01R31/28 ,  G06F11/30

CPC分类号： G06F11/2221 ,  G01R31/318385 ,  G01R31/318547

摘要： An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme. In one embodiment, generating the pseudo-random test patterns includes multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for the peripheral devices.

摘要翻译： 一种装置和方法提供了具有耦合到处理器核心的并行扫描寄存器的多个外围设备的算术内置自检（ABIST），全部在集成电路内。 使用处理器核心的数据路径，操作逻辑为外围设备生成伪随机测试模式，采用混合同余产生方案。 在一个实施例中，生成伪随机测试模式包括将紧邻在前的迭代中生成并存储在第一寄存器中的2n位伪随机数的n个最低有效位乘以存储在第二寄存器中的n位乘法器常数 注册以产生2n位乘积，将2n位乘积加到存储在具有2n个位置的累加器的n个最低有效位置中的2n位伪随机数的n个最高有效位，以产生新的2n位伪随机数， 用于当前迭代的随机数，并且输出新的2n位伪随机数的n个最低有效位作为外围设备的n比特伪随机测试向量。

公开(公告)号：US20050060626A1

公开(公告)日：2005-03-17

申请号：US10777443

申请日：2004-02-10

申请人： Janusz Rajski ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Jerzy Tyszer

IPC分类号： G01R31/3185 ,  G06F11/267 ,  G06F11/00 ,  G01R31/00 ,  G01R31/28

CPC分类号： G06F11/2221 ,  G01R31/318385 ,  G01R31/318547

摘要： In one embodiment, an IC with an embedded processor core, peripheral devices, and associated multiple scan chains, is provided with microcode that implements an arithmetic pseudo-random number generator and an arithmetic deterministic test vector generator, when executed by the embedded processor core, generates 2-D pseudo-random and deterministic test vectors for testing the peripheral devices respectively. The IC is further provided with microcode that implements an arithmetic test response compactor, which when executed by the embedded processor core, compacts test responses of the peripheral devices into a signature. The IC further includes a test port register and microcode that implements a number of ABIST instructions.

摘要翻译： 在一个实施例中，具有嵌入式处理器核心，外围设备和相关联的多个扫描链的IC提供有实现算术伪随机数发生器和算术确定性测试向量生成器的微代码，当由嵌入式处理器核心执行时， 产生用于测试外围设备的2-D伪随机和确定性测试向量。 IC还具有实现算术测试响应压缩器的微代码，当被嵌入式处理器核心执行时，压缩器将外围设备的测试响应压缩成签名。 该IC还包括一个测试端口寄存器和实现一些ABIST指令的微码。

公开(公告)号：US5991909A

公开(公告)日：1999-11-23

申请号：US730066

申请日：1996-10-15

申请人： Janusz Rajski ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Jerzy Tyszer

IPC分类号： G01R31/3181 ,  G01R31/3183 ,  G01R31/28

CPC分类号： G01R31/318335 ,  G01R31/31813 ,  G01R31/318385

摘要： A parallel decompressor capable of concurrently generating in parallel multiple portions of a deterministic partially specified data vector is disclosed. The parallel decompressor is also capable of functioning as a PRPG for generating pseudo-random data vectors. The parallel decompressor is suitable for incorporation into BIST circuitry of ICs. For BIST circuitry with multiple scan chains, the parallel decompressor may be incorporated without requiring additional flip-flops (beyond those presence in the LFSR and scan chains). In one embodiment, an incorporating IC includes boundary scan design compatible with the IEEE 1194.1 standard. Multiple ones of such ICs may be incorporated in a circuit board. Software tools for generating ICs with boundary scan having BIST circuitry incorporated with the parallel decompressor, and for computing the test data seeds for the deterministic partially specified test vectors are also disclosed.

摘要翻译： 公开了能够同时并行地生成确定性部分指定的数据向量的多个部分的并行解压缩器。 并行解压缩器还能够用作生成伪随机数据向量的PRPG。 并行解压缩器适用于集成到IC的BIST电路中。 对于具有多个扫描链的BIST电路，可以并入并行解压缩器，而不需要额外的触发器（超出在LFSR和扫描链中的存在）。 在一个实施例中，并入IC包括与IEEE 1194.1标准兼容的边界扫描设计。 这些IC中的多个可以并入电路板中。 还公开了用于生成具有并入解压缩器的BIST电路的边界扫描的IC以及用于计算用于确定性部分指定的测试向量的测试数据种子的软件工具。

公开(公告)号：US5991898A

公开(公告)日：1999-11-23

申请号：US814042

申请日：1997-03-10

申请人： Janusz Rajski ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Jerzy Tyszer

IPC分类号： G01R31/3185 ,  G06F11/267 ,  G06F13/00

CPC分类号： G06F11/2221 ,  G01R31/318385 ,  G01R31/318547

摘要： An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme. In one embodiment, generating the pseudo-random test patterns includes multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for the peripheral devices.

摘要翻译： 一种装置和方法提供了具有耦合到处理器核心的并行扫描寄存器的多个外围设备的算术内置自检（ABIST），全部在集成电路内。 使用处理器核心的数据路径，操作逻辑为外围设备生成伪随机测试模式，采用混合同余产生方案。 在一个实施例中，生成伪随机测试模式包括将紧邻在前的迭代中生成并存储在第一寄存器中的2n位伪随机数的n个最低有效位乘以存储在第二寄存器中的n位乘法器常数 注册以产生2n位乘积，将2n位乘积加到存储在具有2n个位置的累加器的n个最低有效位置中的2n位伪随机数的n个最高有效位，以产生新的2n位伪随机数， 用于当前迭代的随机数，并且输出新的2n位伪随机数的n个最低有效位作为外围设备的n比特伪随机测试向量。