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公开(公告)号：US07653851B2
公开(公告)日：2010-01-26
申请号：US12412267
申请日：2009-03-26
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译： 公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。
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公开(公告)号：US07523372B2
公开(公告)日：2009-04-21
申请号：US11895845
申请日：2007-08-27
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译： 公开了用于自动合成移相器的方法。 移相器包括用于消除驱动并行扫描链的伪随机测试图形发生器特征的结构依赖性的影响的电路。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。
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公开(公告)号：US07512508B2
公开(公告)日：2009-03-31
申请号：US11221395
申请日：2005-09-06
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for computing and analyzing integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.
摘要翻译： 本文公开了用于计算和分析集成电路产量和质量的方法，装置和系统。 例如，在本文公开的一个示例性方法中，从设计用于电子设备中的功能使用的集成电路的处理测试响应接收信息。 在该实施例中，该信息表示在集成电路测试期间观察到的集成电路故障以及导致集成电路故障的可能的产量限制因素。 通过统计分析接收的信息来确定集成电路中的一个或多个可能的屈服限制因素实际引起集成电路故障的概率。 报告了一个或多个可能的屈服限制因素实际上导致集成电路故障的概率。 还公开了包括用于使计算机执行任何所述方法的计算机可执行指令的有形计算机可读介质。
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公开(公告)号：US07437636B2
公开(公告)日：2008-10-14
申请号：US11265488
申请日：2005-11-01
申请人： Janusz Rajski , Abu Hassan , Robert Thompson , Nagesh Tamarapalli
发明人： Janusz Rajski , Abu Hassan , Robert Thompson , Nagesh Tamarapalli
CPC分类号： G01R31/318594 , G01R31/31858
摘要： Exemplary schemes for multi-frequency at-speed logic Built-In Self Test (BIST) are provided. For example, certain schemes allow at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. Some of the disclosed schemes are also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. In particular embodiments, the loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. In certain embodiments, only the capture cycle is performed at the corresponding system timing. In some embodiments, a programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.
摘要翻译： 提供了多频率高速逻辑内置自检（BIST）的示范方案。 例如，某些方案允许对由外部或片上产生的时钟信号控制的非常高频率的集成电路进行高速测试。 所公开的方案中的一些也适用于具有可以是相同频率或不同频率的多个时钟域的电路的测试。 在特定实施例中，扫描链的加载和卸载与各个域之间的逻辑的速度测试分离，并且可以以比速度测试更快或更慢的频率进行。 在某些实施例中，在对应的系统定时仅执行捕获周期。 在一些实施例中，可编程捕获窗口使得可以在时钟域之间没有时钟偏移的负面影响的情况下测试每个域内和域间的速度。
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公开(公告)号：US20060066339A1
公开(公告)日：2006-03-30
申请号：US11221395
申请日：2005-09-06
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
IPC分类号： G01R31/26
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.
摘要翻译： 本文公开了用于计算，分析和改进集成电路产量和质量的方法，装置和系统。 例如，在本文公开的一个示例性方法中，从设计用于电子设备中的功能使用的集成电路的处理测试响应中接收信息。 在该实施例中，该信息表示在集成电路测试期间观察到的集成电路故障以及导致集成电路故障的可能的产量限制因素。 通过统计分析接收的信息来确定集成电路中的一个或多个可能的屈服限制因素实际上引起集成电路故障的概率。 报告了一个或多个可能的屈服限制因素实际上导致集成电路故障的概率。 还公开了包括用于使计算机执行任何所述方法的计算机可执行指令的有形计算机可读介质。
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公开(公告)号：US20060053357A1
公开(公告)日：2006-03-09
申请号：US11221373
申请日：2005-09-06
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, design defect extraction rules are derived at least partially from a set of design manufacturing rules. Potential defects are extracted from a representation of an integrated circuit layout using the design defect extraction rules. Circuit test stimuli applied during one or more circuit tests are determined. Test responses resulting from the applied circuit tests are evaluated to identify integrated circuits that fail and to identify the occurrence in the failing integrated circuits of one or more potential types of defects associated with the applied circuit tests. Information concerning the repetitive identification in the failing integrated circuits of the occurrence of potential types of defects is collected and analyzed to determine the likelihood of potential types of defects being present in integrated circuits manufactured in accordance with the layout.
摘要翻译： 本文公开了用于测试，分析和提高集成电路产量和质量的方法，装置和系统。 例如，在一个示例性实施例中，至少部分地从一组设计制造规则导出设计缺陷提取规则。 使用设计缺陷提取规则从集成电路布局的表示中提取潜在缺陷。 确定在一个或多个电路测试期间施加的电路测试刺激。 评估由应用电路测试产生的测试响应，以识别故障的集成电路，并识别故障集成电路中与应用电路测试相关的一种或多种潜在类型的缺陷的发生。 收集和分析关于发生潜在类型缺陷的故障集成电路中的重复识别的信息，以确定存在于根据布局制造的集成电路中的潜在类型的缺陷的可能性。
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公开(公告)号：US06920597B2
公开(公告)日：2005-07-19
申请号：US10209817
申请日：2002-07-31
IPC分类号： G01R31/3187 , G06F17/50 , G01R31/28
CPC分类号： G06F17/5045 , G01R31/318385 , G01R31/3187
摘要： A built-in-self-test (BIST) circuit is discussed for selecting tristate nets with substantially uniform distribution using a tristate testing control device (TTCD). The circuit allows the deterministic testing of tristate nets in the context of pseudo-random BIST. A feedback shift register is described that activates a single tristate or set of tristate at a time in order to avoid bus contention. Another TTCD embodiment uses a counter and decoder. A test mode switching unit (TMSU) coupled between the TTCD and the tristate net selects test or functional mode for tristate enables. Parallel multiplexers are discussed as one embodiment of a TMSU. Another TMSU embodiment describes even better test coverage. A method, which may be performed on a distributed computer system, is discussed for identifying tristate nets within a net-list and adding a TTCD and a TMSU to the net-list.
摘要翻译： 讨论了使用三态测试控制装置（TTCD）来选择具有基本均匀分布的三态网络的内置自测试（BIST）电路。 该电路允许在伪随机BIST的上下文中对三态网进行确定性测试。 描述了反馈移位寄存器，以一次激活单个三态或一组三态，以避免总线争用。 另一TTCD实施例使用计数器和解码器。 耦合在TTCD和三态网之间的测试模式切换单元（TMSU）为三态使能选择测试或功能模式。 并行多路复用器作为TMSU的一个实施例进行讨论。 另一个TMSU实施例描述了甚至更好的测试覆盖。 讨论了可以在分布式计算机系统上执行的方法，用于识别网络列表内的三态网络，并将TTCD和TMSU添加到网络列表。
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公开(公告)号：US08438438B2
公开(公告)日：2013-05-07
申请号：US12948460
申请日：2010-11-17
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318569
摘要： Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.
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公开(公告)号：US08301414B2
公开(公告)日：2012-10-30
申请号：US11772648
申请日：2007-07-02
申请人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
发明人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
CPC分类号： G01R31/318547 , G06F11/267
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media comprising lists of fault candidates identified by any of the disclosed methods or circuit descriptions created or modified by the disclosed methods are provided.
摘要翻译： 本文公开了用于执行故障诊断的方法，装置和系统。 在某些公开的实施例中，提供了用于从压缩测试响应诊断故障的方法。 例如，在一个示例性实施例中，接收至少部分基于扫描的测试电路和压实器的电路描述，用于压缩在待测电路中捕获的测试响应。 确定由压实机对被测电路中捕获的测试响应执行的变换功能。 用于评估未压缩测试响应的诊断程序被修改为并入其中的变换功能的修改的诊断过程。 还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。 同样地，提供了包括通过由所公开的方法创建或修改的任何公开的方法或电路描述所识别的故障候选列表的计算机可读介质。
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10.发明授权Fault dictionaries for integrated circuit yield and quality analysis methods and systems 有权集成电路产品和质量分析方法和系统的故障字典公开(公告)号：US07987442B2
公开(公告)日：2011-07-26
申请号：US11221394
申请日：2005-09-06
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern. Further, the one or more fault dictionaries in one embodiment are generated by: (a) for a first defect candidate, storing one or more first indicators indicative of test patterns detecting the first defect candidate, and (b) for a second defect candidate, storing at least a second indicator indicative of the test patterns that detect the second defect candidate, the second indicator comprising a bit mask that indicates which of the test patterns detecting the first defect candidate also detect the second defect candidate.
摘要翻译： 本文公开了用于测试，分析和提高集成电路产量和质量的方法，装置和系统。 例如，在一个示例性实施例中，生成用于从相应的观察点组合识别一个或多个缺陷候选的一个或多个故障字典。 在该示例性方法中，观察点组合表示在应用相应测试图案时捕获故障测试值的被测电路的观察点。 此外，一个实施例中的一个或多个故障字典通过以下方式产生：（a）对于第一缺陷候选，存储指示检测第一缺陷候选的测试图案的一个或多个第一指示符，以及（b）对于第二缺陷候选， 存储指示检测第二缺陷候选的测试图案的至少第二指示符，第二指示符包括指示检测第一缺陷候选的哪个测试图案还检测第二缺陷候选的位掩码。
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