公开(公告)号：US5313469A

公开(公告)日：1994-05-17

申请号：US75629

申请日：1993-06-11

申请人： Saman Adham ,  Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab

发明人： Saman Adham ,  Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab

IPC分类号： G01R31/3183 ,  G01R31/28

CPC分类号： G01R31/318321

摘要： A self-testable digital integrator comprises binary adding apparatus and storage apparatus. The adding apparatus and the storage apparatus are functionally interconnected such that the storage apparatus feeds digital words to the adding apparatus for addition thereof and the adding apparatus feeds resulting digital words to the storage apparatus for storage thereof to perform a digital integration operation. The digital integrator further comprises a first combinational network responsive to a first state of a test mode signal to feed an external input signal to the adding apparatus for integration thereof, and responsive to a second state of the test mode signal to feed to the adding apparatus a test pattern signal derived from selected bias of the digital words fed from the adding apparatus to the storage apparatus. The digital integrator also comprises a second combinational network responsive to the second state of the test mode signal to feed back a carry-out bit of the adding apparatus to a carry-in port of the adding apparatus for test result compaction. The digital integrator optionally comprises a third combinational network responsive to the second state of the test mode signal to feed a carry-out bit of the adding apparatus to the first combinational network, the first combinational network being responsive to the second state of the test mode signal and to the carry-out bit to modify the test pattern signal. The self-testable digital integrator is particularly useful as a component of a digital decimator used to decimate Double Integration Sigma Delta modulation signals.

摘要翻译： 一种可自检的数字积分器包括二进制加法装置和存储装置。 所述添加装置和所述存储装置在功能上互连，使得所述存储装置将数字字馈送到所述添加装置以添加，并且所述添加装置将所生成的数字字馈送到所述存储装置以进行存储以进行数字集成操作。 数字积分器还包括响应于测试模式信号的第一状态的第一组合网络，以将外部输入信号馈送到加法装置以进行积分，并响应于测试模式信号的第二状态馈送到添加装置 从从加法装置馈送到存储装置的数字字的选定偏置导出的测试图案信号。 数字积分器还包括响应于测试模式信号的第二状态的第二组合网络，以将加法装置的进位位反馈到用于测试结果压缩的加法装置的进位端口。 数字积分器可选地包括响应于测试模式信号的第二状态的第三组合网络，以将加法装置的进位位馈送到第一组合网络，第一组合网络响应于测试模式的第二状态 信号和进位位修改测试码信号。 自检数字积分器作为用于抽取双积分Sigma Delta调制信号的数字抽取器的组件特别有用。

公开(公告)号：US08290738B2

公开(公告)日：2012-10-16

申请号：US13049844

申请日：2011-03-16

申请人： Xijiang Lin ,  Dariusz Czysz ,  Mark Kassab ,  Grzegorz Mrugalski ,  Janusz Rajski ,  Jerzy Tyszer

发明人： Xijiang Lin ,  Dariusz Czysz ,  Mark Kassab ,  Grzegorz Mrugalski ,  Janusz Rajski ,  Jerzy Tyszer

IPC分类号： G06F19/00

CPC分类号： G01R31/318575

摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.

摘要翻译： 以下公开了用于在集成电路测试期间降低功耗的方法，装置和系统的代表性实施例。 所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（EDT）架构）集成）。 在所公开的实施例中，具有可编程测试刺激选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。 还公开了可以用于产生用于与任何所公开的实施例一起使用的测试图案的示例性测试图形生成方法。

公开(公告)号：US07900104B2

公开(公告)日：2011-03-01

申请号：US12405409

申请日：2009-03-17

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/28

CPC分类号： G01R31/318335 ,  G01R31/318371 ,  G01R31/318547

摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

摘要翻译： 一种用于压缩被测电路中扫描链应用的测试图案的方法。 该方法包括生成与扫描链内的扫描单元相关联的符号表达式。 通过将变量分配给提供给被测电路的外部输入通道上的位来创建符号表达式。 使用符号仿真，将变量应用于解压缩器以获取符号表达式。 使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障。 通过将测试立方体中的分配值与与相应扫描单元相关联的符号表达式进行等价来表示一组方程式。 求解等式以获得压缩测试图案。

公开(公告)号：US07877656B2

公开(公告)日：2011-01-25

申请号：US12352994

申请日：2009-01-13

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/28

CPC分类号： G01R31/318335 ,  G01R31/31813 ,  G01R31/318547

摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.

摘要翻译： 在测试电路中将测试图案应用于扫描链的方法。 该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。 取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。 执行解压缩的电路包括解压缩器，例如适于接收压缩的比特测试模式的线性反馈状态机。 解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。 电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并适于接收解压缩的测试图案。

公开(公告)号：US20090228749A1

公开(公告)日：2009-09-10

申请号：US12396377

申请日：2009-03-02

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318547

摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

摘要翻译： 一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。 所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。 在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。 该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。 第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。 第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。 其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

公开(公告)号：US07509546B2

公开(公告)日：2009-03-24

申请号：US11523111

申请日：2006-09-18

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G06F11/00

CPC分类号： G01R31/318335 ,  G01R31/318371 ,  G01R31/318547

摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

公开(公告)号：US07478296B2

公开(公告)日：2009-01-13

申请号：US10354633

申请日：2003-01-29

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/28

CPC分类号： G01R31/318335 ,  G01R31/31813 ,  G01R31/318547

摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.

摘要翻译： 在测试电路中将测试图案应用于扫描链的方法。 该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。 取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。 执行解压缩的电路包括解压缩器，例如适于接收压缩的比特测试模式的线性反馈状态机。 解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。 电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并且适于接收解压缩的测试图案。

公开(公告)号：US20070234157A1

公开(公告)日：2007-10-04

申请号：US11709071

申请日：2007-02-20

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Grzegorz Mrugalski ,  Mark Kassab ,  Wu-Tung Cheng

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Grzegorz Mrugalski ,  Mark Kassab ,  Wu-Tung Cheng

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318547 ,  G01R31/318563 ,  G01R31/318566

摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

摘要翻译： 这里公开了所谓的“X-press”测试响应压实机的示例性实施例。 所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。 所公开技术的某些实施例提供约1000x的压实比。 所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。 扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。 本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

公开(公告)号：US07260591B2

公开(公告)日：2007-08-21

申请号：US10781031

申请日：2004-02-17

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G06F7/58

CPC分类号： G06F7/584 ,  G06F2207/583 ,  H03K3/84

摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.

摘要翻译： 用于合成诸如线性反馈移位寄存器（LFSR）或细胞自动机（CA）的高性能线性有限状态机（LFSM）的方法和装置。 给定电路的特征多项式，该方法获得原始的LFSM电路，如I型或II型LFSR。 然后确定原始电路内的反馈连接。 随后，可以以使原始电路的特性保留在修改的LFSM电路中的方式来应用移动反馈连接的多个变换。 特别地，如果原始电路由原始特征多项式表示，则该方法保留修改电路中原始电路的最大长度特性，并使修改电路能够产生与原始电路相同的m序列。 通过各种转换，可以创建一个修改后的LFSM电路，通过较短的反馈连接线路提供更高的性能，更低的逻辑电平和更低的内部扇出。

公开(公告)号：US07111209B2

公开(公告)日：2006-09-19

申请号：US10355941

申请日：2003-01-31

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/28

CPC分类号： G01R31/318335 ,  G01R31/318371 ,  G01R31/318547

摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.