公开(公告)号：US20210365376A1

公开(公告)日：2021-11-25

申请号：US16880248

申请日：2020-05-21

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/0815 ,  G06F12/0804

Abstract: Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.

公开(公告)号：US20210117327A1

公开(公告)日：2021-04-22

申请号：US17135341

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0862 ,  G06F13/16

Abstract: Techniques for implementing and/or operating an apparatus, which includes a memory system coupled to a processing system via a memory bus. The memory system includes hierarchical memory levels and a memory controller. The memory controller receives a memory access request at least in part by receiving an address parameter indicative of a memory address associated with a data block from the memory bus during a first clock cycle and receiving a context parameter indicative of context information associated with current targeting of the data block from the memory bus during a second clock cycle, instructs the memory system to output the data block to the memory bus based on the memory address indicated in the address parameter, and predictively controls data storage in the hierarchical memory levels based at least in part on the context information indicated in the context parameter of the memory access request.