公开(公告)号：US11210019B2

公开(公告)日：2021-12-28

申请号：US15684773

申请日：2017-08-23

Applicant: Micron Technology, inc.

Inventor： Dean D. Gans

IPC: G06F3/06 ,  G06F12/1009

Abstract: Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.

公开(公告)号：US11209981B2

公开(公告)日：2021-12-28

申请号：US17033341

申请日：2020-09-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Shunichi Saito

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10

Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

公开(公告)号：US11189334B2

公开(公告)日：2021-11-30

申请号：US16198433

申请日：2018-11-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans

IPC: G11C11/4076 ,  H03K5/156

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a multi-bit duty cycle monitor. A clock signal may be provided to a memory in order to synchronize one or more operations of the memory. The clock signal may have a duty cycle which is adjusted by a duty cycle adjustor of the memory. The duty cycle of the adjusted clock signal may be monitored by a multi-bit duty cycle monitor. The multi-bit duty cycle monitor may provide a multi-bit signal which indicates if the duty cycle of the adjusted clock signal is above or below a target duty cycle value (or if the duty cycle is outside tolerances around the target duty cycle). The multi-bit duty cycle monitor may provide the multi-bit signal while access operations of the memory are occurring.

公开(公告)号：US11150821B2

公开(公告)日：2021-10-19

申请号：US16543467

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F13/16

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

公开(公告)号：US20210280236A1

公开(公告)日：2021-09-09

申请号：US17328419

申请日：2021-05-24

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans

IPC: G11C11/406 ,  G11C16/34

Abstract: A method of operating a memory device is provided, comprising determining a number of operations corresponding to a memory location during a first timing period; and scheduling an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold. A memory device is provided, comprising a memory including a memory location; and circuitry configured to: determine a number of operations corresponding to the memory location during a first timing period; and schedule an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold.

公开(公告)号：US11037617B2

公开(公告)日：2021-06-15

申请号：US16530092

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans

IPC: G11C11/406 ,  G11C16/34

Abstract: A method of operating a memory device is provided, comprising determining a number of operations corresponding to a memory location during a first timing period; and scheduling an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold. A memory device is provided, comprising a memory including a memory location; and circuitry configured to: determine a number of operations corresponding to the memory location during a first timing period; and schedule an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold.

公开(公告)号：US10910037B2

公开(公告)日：2021-02-02

申请号：US16152306

申请日：2018-10-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  John D. Porter

IPC: G06F3/06 ,  G06F13/40 ,  G11C11/4076 ,  G11C11/4074 ,  G06F13/16

Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

公开(公告)号：US10832748B2

公开(公告)日：2020-11-10

申请号：US16666045

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C8/12 ,  G06F12/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4093

Abstract: Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.

公开(公告)号：US20200312387A1

公开(公告)日：2020-10-01

申请号：US16853917

申请日：2020-04-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Daniel C. Skinner

IPC: G11C7/10

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

公开(公告)号：US20200294562A1

公开(公告)日：2020-09-17

申请号：US16886109

申请日：2020-05-28

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

IPC: G11C7/22 ,  G06F13/36 ,  G11C7/10

Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.