公开(公告)号：US20220368356A1

公开(公告)日：2022-11-17

申请号：US17302228

申请日：2021-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins

IPC: H03M13/37 ,  G06F7/544

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate an error-reduced version of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate an error-reduced version of encoded data for an error correction coding (ECC) decoder, e.g., to facilitate decoding of the error-reduced version of encoded data at the decoder. In this manner, neural networks or recurrent neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by reducing errors present in encoded data due to storage or transmission.

公开(公告)号：US20220287037A1

公开(公告)日：2022-09-08

申请号：US17655742

申请日：2022-03-21

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04W72/04 ,  H04W72/08 ,  H04B10/2575

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system may allocate the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US11387976B2

公开(公告)日：2022-07-12

申请号：US16718930

申请日：2019-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

IPC: H04L5/14 ,  H04B1/525 ,  H04B7/06 ,  H04W4/70 ,  H04B7/026 ,  H04W4/40 ,  H04B7/08 ,  H04W76/14 ,  H04L5/00 ,  H04L25/02

Abstract: Examples described herein include apparatuses and methods for full duplex device-to-device cooperative communication. Example systems described herein may include self-interference noise calculators. The output of a self-interference noise calculator may be used to compensate for the interference experienced due to signals transmitted by another antenna of the same wireless device or system. In implementing such a self-interference noise calculator, a selected wireless relaying device or wireless destination device may operate in a full-duplex mode, such that relayed messages may be transmitted as well as information from other sources or destinations during a common time period (e.g., symbol, slot, subframe, etc.).

公开(公告)号：US20220147810A1

公开(公告)日：2022-05-12

申请号：US17092033

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Marko Vitez ,  Eugenio Culurciello ,  Jaime Cummins ,  Andre Xian Ming Chang

IPC: G06N3/08 ,  G06N3/04 ,  G06F8/41

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A computing device running a compiler can interact and/or probe an integrated circuit device to identify hardware characteristics of the integrated circuit device in performing matrix computations. The compiler can generate and optimize a result of compilation from a description of an artificial neural network based at least in part on the hardware characteristics of the integrated circuit device. The result of compilation can include first data representative of parameters of the artificial neural network and second data representative of instructions executable by the integrated circuit device to generate an output of the artificial neural network based on the first data and an input to the artificial neural network.

公开(公告)号：US20220147808A1

公开(公告)日：2022-05-12

申请号：US17092013

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Andre Xian Ming Chang ,  Aliasger Tayeb Zaidy ,  Eugenio Culurciello ,  Jaime Cummins ,  Marko Vitez

IPC: G06N3/08 ,  G06N3/063 ,  G06F9/50 ,  G06F17/16 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler can convert a description of an artificial neural network into a generic result of compilation according to a specification of a generic Deep Learning Accelerator and then map the first result of compilation into a platform-specific result according to a specification of a specific hardware platform of Deep Learning Accelerators. The platform-specific result can be stored into the RAM of the integrated circuit device to enable the integrated circuit device to autonomously perform the computation of the artificial neural network in generating an output in response to an input to the artificial neural network.

公开(公告)号：US11284394B2

公开(公告)日：2022-03-22

申请号：US16893740

申请日：2020-06-05

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04W72/04 ,  H04W72/08 ,  H04B10/2575 ,  H04W88/08 ,  H04L67/12

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system may allocate the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US11159188B2

公开(公告)日：2021-10-26

申请号：US16432766

申请日：2019-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jeremy Chritz ,  Jaime Cummins ,  Tamara Schmitz

IPC: H04B1/04 ,  H04L1/00 ,  H03M13/15 ,  H04L5/14 ,  H04L5/00 ,  H04B1/12 ,  H04B1/525

Abstract: Examples described herein include methods, devices, and systems which may compensate input data for non-linear power amplifier noise to generate compensated input data. In compensating the noise, during an uplink transmission time interval (TTI), a switch path is activated to provide amplified input data to a receiver stage including a coefficient calculator. The coefficient calculator may calculate an error representative of the noise based partly on the input signal to be transmitted and a feedback signal to generate coefficient data associated with the power amplifier noise. The feedback signal is provided, after processing through the receiver, to a coefficient calculator. During an uplink TTI, the amplified input data may also be transmitted as the RF wireless transmission via an RF antenna. During a downlink TTI, the switch path may be deactivated and the receiver stage may receive an additional RF wireless transmission to be processed in the receiver stage.

公开(公告)号：US11139845B2

公开(公告)日：2021-10-05

申请号：US16935699

申请日：2020-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04B1/62 ,  H04B1/04 ,  H04L25/03 ,  H04L1/00

Abstract: Systems, methods, and apparatuses for wireless communication are described. Input data for in-phase branch/quadrature branch (I/Q) imbalance or mismatch may be compensated for or non-linear power amplifier noise may be used to generate compensated input data. In some examples, a transmitter may be configured to transmit communications signaling via a first antenna, the transmitter including a filter configured for digital mismatch correction; a receiver may be configured to receive communications signaling via a second antenna; and a switch may be configured to selectively activate a first switch path to couple the transmitter and the first antenna and a second switch path to couple the receiver and the transmitter to provide communications signaling received via the transmitter as feedback for the filter through the receiver.

公开(公告)号：US20210089637A1

公开(公告)日：2021-03-25

申请号：US17024462

申请日：2020-09-17

Applicant: Micron Technology, Inc.

Inventor： Jaime Cummins ,  Jeremy Chritz ,  Tamara Schmitz ,  Robert F. Gazdzinski

IPC: G06F21/32 ,  H04L29/08 ,  H04L29/06

Abstract: Methods and apparatus for biometric data maintenance, access and distribution across two or more experiential and/or network domains. In one embodiment, a 5G NR-based network architecture is provided which allows ultra-low latency and effectively user-imperceptible biometric data use for e.g., authentication and maintenance of user state across multiple domains via multiple constituent user devices (e.g., UEs). The network architecture includes both (i) a distributed biometric database (BDB) model wherein relevant biometric data for individuals/UEs is intelligently cached in various portions of the distributed database, and (ii) centralized and local BAEs (biometric analytics entities) which manage the aforementioned intelligent caching, as well as network configuration using one or both of 5G NR network “slicing” and CU/DU split options to optimize end-user biometric-related applications such as those providing identification/authentication, AR functions, VR functions or yet others.

公开(公告)号：US10956315B2

公开(公告)日：2021-03-23

申请号：US16043921

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: G06F12/02 ,  G06F12/0893 ,  G06F12/0864 ,  G06F12/06

Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.